- 學位論文
次取樣鎖相迴路輔以基於時間數位轉換器之鎖頻迴路
A Sub-Sampling Phase-Locked Loop with a TDC-Based Frequency-Locked Loop
摘要
近年來，隨著無線通訊系統的日趨普及，特別是第五代行動通訊技術(5G)的興起，對於資料的傳輸速度與規格要求也變得更為嚴峻。在這樣的應用中，鎖相迴路通常扮演著關鍵角色，除了需提供高頻的時脈訊號作為主要的系統傳輸訊號外，對於該訊號本身的雜訊大小也有著嚴峻的規格要求。過大的雜訊將嚴重限制資訊傳輸的正確性，如何實現低雜訊的鎖相迴路也因此是近年來學術上相當熱門的研究題目。 在眾多低雜訊鎖相迴路的架構中，以次取樣鎖相迴路其發展相對成熟，在架構上也相對簡單。相較傳統鎖相迴路，次取樣技巧最大的突破在於移除回授路徑上的除頻器，迴路中電路的雜訊到輸出的轉移函數將不再被乘上除頻器除數的平方倍，因而能大幅抑制頻寬內的雜訊大小。然而，正因為將除頻器移除，也導致該架構的頻率鎖定範圍變窄，需搭配另一組頻率鎖定迴路輔助頻率鎖定。儘管近年來有不少文獻旨在加速頻率鎖定過程，鎖定時間仍落於數個微秒的數量級上，仍有優化空間。 本論文實現一個整數型次取樣鎖相迴路，除了保留原本架構低雜訊的優勢，同時提出一個以時間數位轉換器為核心的鎖頻迴路架構，提供整體迴路更為穩定、快速的頻率鎖定機制。此系統以TSMC 90奈米CMOS製程實現，核心電路面積為0.438 mm2。整體電路操作在1.2伏(類比電路)與1伏(數位電路)的供應電壓下。當輸入參考頻率給定為40 MHz，並且輸出頻率穩定鎖在2.4 GHz時，量測到在200 kHz頻率偏移下，頻寬內的相位雜訊為-108 dBc/Hz，並且參考突波為-63.8 dBc。以頻率偏移10 kHz至100 MHz作為頻率積分範圍，輸出訊號的方均根抖動則為495.7 fs。整體功耗為4.41 mW。最後，在不同的模擬條件下注入不同的干擾訊號，或是改變輸出頻率從2.4 GHz切換至2.44 GHz，模擬結果顯示整體鎖頻迴路平均僅需160奈秒的頻率鎖定時間。
並列摘要
Recently, as the wireless system, especially for 5G techniques, gets more prevailing, the demand for data’s transmission rate and specification requirements get more stringent. In such applications, the phase-locked loop (PLL) usually plays a crucial role in need of providing clock signals with high speed and ultra-low phase noise. Too large phase noise will severely degrade the correctness of data transmission. Therefore, it is a popular research topic to realize a low-noise PLL nowadays. Among all low-noise PLLs, the sub-sampling PLL (SSPLL) develops relatively well and has a much simpler architecture. Compared to traditional PLLs, the major breakthrough of sub-sampling techniques lies in the removal of the divider in the feedback path. So, noise of circuits in the loop will no longer be multiplied by the square of the divider’s modulus, which drastically suppresses the in-band phase noise. However, due to the removal of the divider, it leads to a much narrower locking range of an SSPLL as well. To overcome this, an additional frequency-locked loop (FLL) is always required. Despite the fact that many recent researches work on speeding up the locking process, the locking time of an FLL falls in the range of several microseconds, which still has room for improvement. This thesis realizes an integer-N SSPLL, which not only retains its low-noise advantage, but also includes a novel FLL topology based on a time-to-digital converter (TDC), which provides a more robust and faster frequency-locking mechanism. The overall system is fabricated in TSMC 90-nm CMOS process. The core area is 0.438 mm2, and circuits are operated with 1.2-V (for analog circuits) and 1-V (for digital circuits) supplies. As the reference frequency is given 40 MHz, and the output frequency is locked at 2.4 GHz, the measured in-band phase noise at 200 kHz offset is -108 dBc/Hz, and the reference spur is -63.8 dBc. Still, integrated with a frequency-offset range from 10 kHz to 100 MHz, the RMS jitter comes to 495.7 fs. The total power consumption is 4.41 mW. At last, the system is simulated by injected with various interferences or changing the output frequency from 2.4 GHz to 2.44 GHz at different simulating conditions, all the simulation results show that the proposed FLL requires the average locking time of only 160 ns.