近年來,系統晶片設計(SoC)成為超大型積體電路的設計趨勢。藉由重覆使用矽智財,SoC的設計方法可以加快系統整合的設計速度。在本篇論文中,我們實現一個適用於無線區域網路的加解密引撆。根據802.11i發展中的規格,CCMP是IEEE802.11i中必須實現的標準。因此,我們在以ARM為基礎之系統晶片平台實現CCMP協定,並提出一個階層式驗證流程以加快系統晶片驗證的速度。在成果中,我們實現一個系統晶片的設計流程,並以有效率的方式產生進階加密標準的Soft/Firm/Hard IP。 在效能的評估方面,我們採用Min-Cut Algorithm針對軟硬體分割的方式進行最佳化的分析。在進階加密標準的硬體方面,我們採用一個低成本/高效率的架構進行硬體的實現。在本篇論文的最後,我們採用Artisan公司標準單元(standard cell library)來實現我們的架構,以便進一步驗證我們的系統晶片設計。
In recent years, SoC becomes the future design trend in VLSI design. Due to the IP reuse, SoC design methodology can enhance the design efficiency in system level integration. In this thesis, we focus on the design and implementation of the Wireless LAN security engine. The ongoing standard in 802.11i, and Counter mode and CBC-MAC Protocol (CCMP) is the mandatory protocol in IEEE 802.11i. Thus, we implement CCMP protocol in ARM-based SoC platform and proposed a hierarchical verification flow to enhance the verification speed. As a result, we can realize SoC design flow and deliver Soft, Firm, Hard IP of AES in an efficient way. In the performance evaluation, we evaluated three different HW/SW implementation methods to realize CCMP protocol by min-cut algorithm. Then, we adopted an ARM-based AES design of [31] to achieve low-area/high-throughput implementation. In this thesis, we propose the design techniques to implement the ARM-based SoC platform in Artisan 0.18um standard cell library.