- 學位論文
子集加總延遲線: 一種能實現超高精度且容易實作在可編程邏 輯陣列上的延遲電路
The subset sum delay line: an ultra-high resolution approach that can be easily implemented in FPGA
摘要
本 論 文 提 出 了 一 種 能 夠 實 作 在 可 編 程 邏 輯 陣 列 (FPGA) 上的高精度 (ps 等級) 可調延遲電路結構，其 原理是藉由把數位電路的邏輯閘視為特性不佳的延遲 線，再藉由演算來把這些元件組合成特性優良解析度高 的延遲電路。此種延遲電路囊括非常多同類型產品缺乏 的優點，除了不依賴特定 FPGA 的架構而容易移植和整 合以外，理論上還能夠提供近乎連續而且有彈性的輸出 範圍，因而擁有非常高的時間解析度，僅受限於 FPGA 電路因電壓與溫度的不穩定性引起的時基誤差 (jitter)。 本文除了提出簡單的介紹與操控演算法之外，還對此 種電路的硬體做了非常深入的理論分析，並且於 Altera Cyclone II FPGA 上示範實做了一個原型，根據實測，其 動態範圍涵蓋 12ns 至 35ns，解析度高達 20ps。
並列摘要
In this work, a new scheme of high precision programmable delay line that can be implemented on FPGA is proposed. The core idea is to treat digital logic cells as poor-quality delay lines, and try to generate accurate latencies via recombina- tion. The proposed architecture possesses many advantages over other products of similar categories. It not only enjoys all the conveniences that results from being possible to be re- alized in FPGAs, but also possess almost continuous output range according to theoretical analysis. These facts make it an excellent timing actuator that can provide resolution all the way beyond than that of any measurement instruments. The resolution is only limited by the jitter resulted from variations in temperature and power supply voltage. Furthermore, the scheme works almost independent of the hardware and can be ported to any FPGA easily. In this thesis we presented a hard- ware scheme, some necessary algorithms, and an in-depth dis- cussion on the behavior of the hardware. In addition, we con- struct a prototype of this programmable delay line in Altera Cyclone II FPGA. According to our experiment, the output range of this prototype covers from 12 ns to 35 ns with 20 ps resolution.