應用於4-350K環境且具有頻寬追蹤之低功耗基於環形架構的鎖相迴路

A 4-350K Low-Power Ring-based Phase-Locked Loop with Bandwidth Tracking

許凱翔(Kai-Xiang Hsu)

指導教授 ： 李泰成

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2024年)

https://doi.org/10.6342/NTU202401663

摘要

本論文介紹了一種設計用於高頻率操作並保持低供應電壓的鎖相迴路（PLL）。此PLL採用雙通道架構，其中比例路徑保持迴路穩定，而積分路徑處理由溫度改變引起的環振盪器頻率變化。採用一個簡單的電路專門用於實現頻寬跟蹤功能。所有偏置電壓均由內部生成，以確保偏置水平完全由操作條件決定。

此PLL採用40納米TSMC CMOS技術實現，佔用核心面積為0.0054 mm2。它能夠在 4 到 353.15 K（-269.15 到 80 攝氏度）的寬廣溫度範圍內有效運行。在室溫下，基於10GHz輸出和0.6V供應電壓，此PLL表現出0.28 mW/GHz的功率效率。此外，對於0.6V供應電壓配置，它實現了低於-220dB的穩定品質因數（FoM）。

關鍵字

鎖相迴路 ； 雙迴路鎖相迴路 ； 負斜率振盪器 ； 頻寬追蹤 ； 量子運算 ； 低溫 CMOS

並列摘要

This thesis introduces a phase-locked loop (PLL) designed to operate at high frequencies while maintaining a low supply voltage. The PLL employs a dual-path architecture: the proportional path maintains loop dynamics, and the integral path compensates for frequency variations in the ring oscillator due to temperature fluctuations. A simple circuit is solely responsible for implementing the bandwidth tracking function. The biases are all generated internally, ensuring that the operating conditions alone determine the bias levels.

The proposed PLL, implemented in 40-nm TSMC CMOS technology, covers a core area of 0.0054 mm2. It operates effectively across a wide temperature range, from 4 K to 353.15 K (-269.15 to 80 oC). The PLL achieves a power efficiency of 0.28 mW/GHz, with a 10-GHz output and a 0.6V supply voltage at room temperature. Furthermore, it achieves a stable figure-of-merit (FoM) lower than -220 dB for the 0.6V supply voltage configuration.

並列關鍵字

Phase-Locked Loop（PLL） ； Dual-Path PLL ； Negative-skew oscillator ； Bandwidth-tracking ； Quantum computing ； cryo-CMOS

參考文獻

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