- 學位論文
微波及毫米波具帶通濾波切換器和功率放大器的研製
Design of Filter-Integrated Switch and Power Amplifier for Microwave and Millimeter-wave Applications
摘要
隨著無線通訊技術的蓬勃發展，射頻積體電路正朝向更高頻率、更廣頻寬及更高的系統整合度之趨勢發展。在無線通訊收發前端電路中，切換器扮演著切換傳送的及接收路徑之角色，帶通濾波器則是過濾使用頻帶外不必要的訊號。值得注意的是：切換器以及帶通濾波器的等效電路中，電容不可或缺的電路元件。在一個強調系統整合及縮小晶片面積以達到高效能且低成本的時代，若可以將此二電路的功能整合成一個單一電路元件，是一個值得研究的課題。 在本論文中，我們利用以上所提及的概念，提出了一個新的電路：具帶通濾波器功能之切換器，簡稱帶通濾波切換器(Filter-Integrated Switch, FIS)。首先我們利用四分之一波長帶通濾波器的電路架構，設計並量測了一個單刀單擲(SPST) 帶通濾波切換器，實現了該理念。此電路是一個用FR4版子製作，中心頻率 1GHz，頻寬參數(BWF)為0.6的切比雪夫帶通律波器設計的單刀單擲開關。此開關的量測結果是本電路的輸入損耗小於2 dB，隔離度大於22 dB。為了將本概念應用於收發機，我們將兩個單刀單擲帶通濾波切換器，合而為一成一個單刀雙擲(SPDT)開關。然而，關閉狀態單刀單擲切換器的阻抗會影響到另一半啟動狀態單刀單擲切換器的輸入損耗。為了克服該問題，我們使用共用共振腔的方法來解決。功率分析也同時提出來預測開關的P1dB 利用四分之一波長帶通濾波器的電路架構來設計帶通濾波切換器有個缺點：就是該電路使用的四分之一波長傳輸線太長以致於佔用相當大的晶片面積。為了解決該問題，我們介紹了微小化帶通濾波單刀雙擲切換器的概念。微小化技術不但可將晶片面積縮小，也可改善切換器的輸入損耗。有兩個毫米波電路使用了微小化的技術來實現該理念。第一個電路是使用 0.15-μm GaAs mHEMT製成，中心頻率於40 GHz的微小化帶通濾波單刀雙擲切換器。量測可得本電路具有帶通濾波器的頻率響應，在30到50 GHz之間，有小於1 dB的輸入損耗，大於12 dB的反射損耗以及大於32 dB 的隔離度。晶片大小為2 mm x 1mm。第二個電路則是使用 0.15-μm GaAs pHEMT製成，中心頻率於50 GHz的微小化帶通濾波切換器。量測結果驗證了本電路具有帶通濾波器的頻率響應，在40到60 GHz之間，有小於1.5 dB的輸入損耗，大於10 dB的反射損耗以及大於22 dB 的隔離度。且與同頻帶同製程但未使用微小化技術的帶通濾波切換器比較，晶片大小由2 mm x 1mm縮小至1.5 mm x 1mm。 另外，為了達到低成本高整合性的無線通訊系統，近年來CMOS功率放大器成為一個熱門的研究課題。本論文最後一個電路是應用於71至76 GHz系統的寬頻功率放大器。此電路使用先進的90-nm CMOS製程，本電路架構採用3級cascode串接的平衡放大器。採用平衡放大器的架構，可以增加電路的輸出功率以及良好的反射損耗。根據量測結果，本電路在68到83 GHz之間，可達到大於17.6 dB的增益，大於15 dB的反射損耗以及大於11.5 dBm的飽和輸出功率(Psat)。
並列摘要
With the development of wireless communication technologies, RF integrated circuits move toward higher frequencies, wider bandwidth, and higher system integration. In wireless communication transceiver front-ends, switch plays an role of switching the transmitting and receiving mode; band-pass filter (BPF) is used to reject to out-of-band signal. It is noted that in the equivalent circuits of switch and BPF, capacitance is one of the essential basic circuit components. Since reduction of chip area is desirable, integration of two circuit functions into a single will be an attractive research topic. In this thesis a new circuit component, called filter-integrated switch (FIS), is proposed. In order to implement this idea, first we design and measure a single-pole-single-throw (SPST) FIS by using quarter-wavelength BPF circuit topology. The circuit is a 1-GHz Chebyshev band-pass SPST FIS with a bandwidth factor 0.6, and it is made by FR4 PC board. The measured insertion loss is lower than 2 dB and isolation is higher than 22 dB. Moreover, to implement this concept in transceiver system, we have to combine two SPST FIS’ into a single-pole-double-throw (SPDT) switch. However, the impedance of the off-state SPST switch will affect the insertion loss of the on-state SPST switch in another half circuit. The sharing resonator is introduced to solve this problem. Power analysis is also presented to predict the P1dB of the switch. The drawback of quarter-wavelength FIS is that the long electrical length of a quarter-wavelength transmission line occupies large chip area. In order to resolve this, the concept of reduced-size FIS SPDT switch is introduced. Size reduction technique can not only reduce the chip area, but also improve the insertion loss of the switch. Two millimeter-wave (MMW) MMIC SPDT SPDT switches have been demonstrated this size reduction technique. The first one is a 40-GHz SPDT switch using 0.15-μm mHEMT process. It has a band-pass filter frequency response and achieves the measured insertion loss, return loss and isolation of better than 1, 12, and 32 dB, respectively, from 30 to 50 GHz with a chip size 2 mm x 1mm. Another one is a 50-GHz SPDT switch using 0.15-μm pHEMT process. It has a band-pass filter frequency response and achieves the measured insertion loss, return loss and isolation of better than 1.5, 10, and 22 dB, respectively, from 40 to 60 GHz. The chip size has been reduced to 1.5 mm x 1 mm compared with the one working at same frequency, using same process but without using size reduction technique (2 mm x 1mm). Moreover, millimeter-wave CMOS PA is an important research topic in recent years for low-cost and high-integration wireless communication systems. The last circuit in the thesis is a broad band PA for the 71-76-GHz system application. The circuit is fabricated in a 90-nm bulk CMOS process. The circuit topology is a balanced three-stages cascode amplifier. The balanced amplifier can achieve higher output power with good return loss. The measured results shows the circuit has small signal gain of better than 17.6 dB, return loss better than 15 dB. The output saturation power is better than 11.5 dBm.