- 學位論文
應用於高速行動通訊之基頻帶寬頻可程式化增益放大器設計
Design of Wideband Programmable Gain Amplifier in High Speed Mobile Communication Baseband Circuit
摘要
本研究提出了應用於高速行動通訊之基頻帶寬頻可程式化增益放大器，採用改良式Cherry-Hooper放大器電路改善電路速度，並引入了主動元件模擬電感的技巧，產生一個零點使得一個極點被相互抵消，進而實現拓展頻寬之效果，並利用電晶體源極衰減線性改善來增加電路的線性度。數位控制訊號為5位元，經過解碼器後轉為控制電阻陣列之信號，並利用電阻陣列來控制整體放大器的增益，整體架構共有6級增益級並包含直流偏移抵銷迴路，總共30個增益級，增益階為1.6 dB。 TSMC 90nm下線製作與實測結果顯示，此提出的可調變增益放大器的頻寬可超過2.4 GHz，可調變增益範圍約為0~40 dB(S21參數，若加上balun loss須平移6dB)，線性度規格OP1dB為-6~-8 dBm(不同增益下)，OIP3為4 dBm，在供應電壓為1.2伏的情況下，消耗功率為6.7mW。晶片面積包含PAD時整體面積為0.99 mm^2，僅考量核心電路面積為0.115 mm^2。
並列摘要
In this thesis, a wideband programmable gain amplifier in high speed mobile communication baseband circuit is present. In order to improve -3dB frequency, modified Cherry-Hooper amplifier is used. Additionally, gate peaking technique produces a zero which can cancel a pole. Considering the performance of linearity, source degeneration with MOS is used in the gain cell. There are 5 bits digital control signals controlling the gain step. The structure of PGA consists of six gain cells and dc offset cancellation loop. The PGA has 30 gain step can be varied in 1.6dB. The proposed PGA is fabricated in TSMC 90nm CMOS process. The measure gain (S21 parameter) is from 0~40dB. The -3dB frequency is about 2.4GHz. The OP1dB is about -6dBm and OIP3 is 4 dBm. The power of PGA core is 6.7 mW under 1.2V supply voltage. The area of the chip including PAD is 0.99 mm^2 and the area of the core PGA is 0.115 mm^2.