扇出型封裝技術的市場趨勢、競爭力與未來發展

近年來，隨著智慧型手機、平板電腦等消費電子產品的日益普及，半導體產業對於微小化、高密度、高效能的封裝技術有著越來越高的需求。除前段製程微縮越來越困難外，5G通訊對高頻寬、低延遲與大量連線的要求，使得通訊晶片必須要有更高的整合性，才能滿足5G通訊提出的效能標準；再加上絕大多數物聯網裝置都有嚴格的成本、能耗與外觀尺寸的限制，通訊晶片業者如果不能利用先進封裝技術，將更多通訊元件、甚至天線整合在單一封裝機構內，形成完整的微型通訊模組，恐怕將難以滿足未來應用市場的需求。此外，為滿足AI人工智慧晶片所需要的高速運算處理能力，將一顆SoC設計切割成chiplet，再用先進封裝技術提供的高密度互聯，將多顆chiplet包在同一個封裝結構內，將會是未來的發展趨勢，而這個趨勢也會讓原本使用不同供應鏈跟設備的前後段半導體製程，變得越來越相似。當然，製程設備與相關材料的費用與成本，也將隨之高漲。其中，晶圓級封裝（WLP）作為一種高效能、低成本、微小化的封裝方式，在市場上也獲得了廣泛應用。然而，晶圓級封裝 (WLP) 也存在一些限制，例如製程複雜度高、封裝高度有限且隨著封裝單位尺寸逐步增大等問題，進一步促使了先進封裝技術從晶圓級封裝(WLP)向面板級封裝（PLP）轉變的趨勢，而其兩種封裝方式，並非零和戰局，而是希望在其間找到最適合的成本效能方案。因此，晶圓代工廠與封裝製造廠因應客戶的高階製程需求，除了發展先進封裝產業，也同時發展面板級封裝技術，以建立不同的ECO system。本論文內容主要在說明扇出型封裝(Fan-out packaging) 的發展沿革，藉由文獻整理回顧分析早期扇出型封裝製程發展歷程、歷年的市場狀況與變化，並對未來可開發的市場契機與技術發展方向提供建議。本研究並針對主要封裝方式，整理封裝產業發展扇出型製程技術的現況與未來機會，提供封裝產業未來發展策略之參考。

關鍵字

晶圓級封裝；扇出型封裝；面板級封裝；小晶片；重構線路層

並列摘要

In recent years, with the increasing popularity of consumer electronic products such as smartphones and tablet computers, the semiconductor industry has increasingly high demand for miniaturized, high-density, and high-efficiency packaging technologies. In addition to the increasingly difficult miniaturization of the front-end process, 5G communication requires high bandwidth, low latency, and many connections, so that communication chips must have higher integration to meet the performance standards proposed by 5G communication. Most IoT devices have strict cost, energy consumption and appearance size restrictions. If communication chip manufacturers cannot use advanced packaging technology, they can integrate more communication components and even antennas into a single packaging mechanism to form a complete miniature communication module, I am afraid that it will be difficult to meet the needs of the future application market. In addition, in order to meet the high-speed computing and processing capabilities required by AI (artificial intelligence) chips, cutting a SoC design into chiplets, and then using the high-density interconnection provided by advanced packaging technology to package multiple chiplets in the same packaging mechanism, will it is the future development trend, and this trend will make the front and rear semiconductor processes that originally use different supply chains and equipment become more and more similar. Of course, the cost of process equipment and related materials will also rise accordingly. Among them, wafer-level packaging (WLP), as a high-efficiency, low-cost, and miniaturized packaging method, has also been widely used in the market. However, wafer-level packaging (WLP) also has some limitations, such as high process complexity, limited package height, and gradually increasing packaging unit size, which further promotes advanced packaging technology from wafer-level packaging (WLP) to the changing trend of panel-level packaging (PLP), and the two packaging methods, are not a zero-sum battle, but hope to find the most suitable cost-effective solution among them. In response to customers' high-level process requirements, wafer foundries and packaging manufacturers not only develop advanced packaging industries, but also develop panel-level packaging technologies to establish different ECO systems. The content of this paper is mainly to explain the development history of fan-out packaging (Fan-out packaging), review and analyze the development history of the early fan-out packaging process, the market conditions and changes over the years, and the market opportunities that can be developed in the future providing advice with directions. This study also explains the status and future opportunities of the fan-out process technology in the packaging industry for the main packaging methods and provides a reference for the future development strategy of the packaging industry.