- 學位論文
考慮擺置效應之一維鰭式場效電晶體標準單元佈局產生
Placement-Aware Layout Generation of One-Dimensional FinFET Standard Cells
摘要
鰭式場效電晶體(FinFET)具有的許多優點，使得他成為製造先進奈米積體電路的最佳選擇。此外，由於一維佈局(one-dimensional layout)相對於二維佈局(two-dimensional layout)具有較高的生產率，通常在先進奈米製程中會優先採用一維佈局。本論文提出一個自動化流程，能夠根據給定的電晶體原理圖(schematics)自動生成相對應的一維鰭式場效電晶體標準單元(standard cell)佈局，除了優化面積、線長、通孔數量及繞線軌道的數量，我們生成的佈局還考慮假性閘極與電源連繫(dummy gate power tying)並且減少使用佔於單元邊界的線(boundary wires)，使得單元間能共享假性閘極以得到緊密的標準單元擺置(placement)。據我們所知，這是第一篇提出考慮擺置效應之一維鰭式場效電晶體標準單元佈局生成的論文。我們利用線性規劃進行有效率的求解，實驗結果顯示此方法的可行性且能夠生成高質量的佈局。
並列摘要
Due to its many advantages, FinFET technology becomes the prominent choice of fabricating advanced nanometer integrated circuits. Moreover, due to its high manufacturability, one-dimensional (1-D) layout is often preferred to its two-dimensional counterpart in advanced technology nodes under the nanometer regime. This thesis proposes a automatic process that generates the layouts of 1-D FinFET standard cells from their transistor schematics. In addition to area, wirelength, the number of vias and routing tracks, dummy gate power tying and boundary wire occupancy minimization are considered to allow inter-cell dummy gate sharing for compact standard cell placement. To the best of our knowledge, this is the first work of layout generation for 1-D FinFET standard cells that considers inter-cell placement effects. Our formulation exploits integer linear programming (ILP) for effective computation. Experimental results show the feasibility of our approach to generate high quality layouts.