使用非破壞性壓力測試預測晶片最小工作電壓

Vmin Prediction Using Nondestructive Stress Test

陳淳(Chun Chen)

指導教授 ： 李建模

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202210116

摘要

我們運用非破壞性壓力測試提出了一個全新的晶片最小工作電壓預測流程，其能避免面積代價並且能減少測試時間。我們將測試 fail-log 經過加總處理成 MMC 數據。我們使用三種策略： CYSO、 PSSY 以及 PSSO 策略來產生 MMC，並且使用 MMC 來預測晶片最小工作電壓。除此之外，我們選出與最小工作電壓相關的重要測試圖樣來減少測試時間。我們使用斯皮爾曼等級相關係數來找出重要的 MMC 索引值，並且使用模擬退火法在可接受的時間之內找出重要的測試圖樣子集合。我們採用線性回歸與極限梯度提昇回歸模型來進行實驗。在先進的 7 奈米與 3 奈米晶片上的實驗結果顯示，使用 CYSO 策略搭配線性回歸模型來預測最小工作電壓可以僅有 4.48 至 8.66 毫伏特的均方根誤差。並且，根據實驗結果，我們的測試圖樣選擇流程可以減少 354 至 948 倍的測試圖樣。我們所提出的流程能夠有比 process monitor 方法還要小的均方根誤差，並且與傳統測試方法相比，有 50 至 62.5 倍的時間加速。

關鍵字

晶片效能預測 ； 非破壞性壓力測試

並列摘要

We propose a novel minimum operating voltage (Vmin) prediction flow using nondestructive stress-test to avoid area overhead and reduce test time. We process stress-test fail-logs and generate summation values, which is called MMC. Three strategies: CYSO, PSCY and PSSO strategies are used to generate MMC. Then, we use MMC to predict Vmin. In addition, we select important test patterns that correlated to Vmin to reduce test time. We use Spearman Correlation to find important MMC-Indices. Also, we use simulated annealing to select important test pattern subsets in an acceptable time. Two regression models, linear regression and XGBoost regression, are adopted in our experiment. Experimental results on advanced 7nm and 3nm chip designs show that the average RMSE of our predict Vmin can be as low as 4.48 mV to 8.66mV by CYSO strategy with linear regression model. Moreover, our test pattern selection flow can have 354 to 948 times test pattern reduction. Our flow gives smaller RMSE than the process monitor flow, and is 50 to 62.5 times faster compared to the conventional testing flow.

並列關鍵字

Chip performance prediction ； Nondestructive stress test

參考文獻

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