應用於低功耗鐵電記憶體之鐵電電容面積比最佳化設計

Area Ratio Optimization for Low-Power FeMFET Memory

陳彥宇(Yen-Yu Chen)

指導教授 ： 胡璧合

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2024年)

https://doi.org/10.6342/NTU202403826

摘要

鐵電電晶體(Ferroelectric Field-Effect Transistor, FeFET)作為一個有潛力的新興記憶體，如何降低其寫入電壓及增加記憶體視窗(Memory Window, MW)是一大挑戰。過去研究指出可以透過使用後段製程（Back-End-of-Line, BEOL）相容鐵電電容與前段製程（Front-End-of-Line, FEOL）電晶體串聯的結構，並調整兩者間的面積比(Area Ratio, AR)來增加記憶體視窗;也有其他研究指出透過使用高介電係數的側壁(Spacer)材料來增加記憶體視窗。然而，過去文獻缺少針對後段鐵電電容與前段電晶體面積比的最佳化探討，因此本論文將研究不同寫入電壓、鐵電參數及側壁材料對鐵電電晶體最佳化面積比的關係，並使用對應的等效電容模型來解釋觀察到的現象。論文最後研究鐵電電晶體陣列(FeFET Array)，探討鐵電電晶體在不同面積比與側壁材料的設計下受寫入干擾(Write Disturbance)的影響。
首先，我們探討鐵電電晶體在側壁材料為Si3N4的情況下，不同寫入電壓、殘餘極化(Remanent Polarization, Pr)及矯頑電場(Coercive Field, Ec)與最佳化面積比(Optimized Area Ratio, AR*)以及最佳化記憶體視窗(Optimized Memory Window, MW*)的關係。我們發現最佳化面積比隨著寫入電壓上升會跟著上升，並且發現部分鐵電參數在高寫入電壓(4.5 V)下其最佳化面積比(AR*) = 1，代表在該情況減小面積比(AR)並不能增加記憶體視窗(MW)。在分析不同的鐵電參數組合及面積比對鐵電記憶體視窗的影響後，研究發現在低寫入電壓(2 V)下，鐵電電晶體在殘餘極化為15 μC/cm^2、矯頑電場為1.2 MV/cm，有最大的最佳化記憶體視窗0.89 V。
本論文接著研究鐵電電晶體在殘餘極化為15 μC/cm^2、矯頑電場為1.2 MV/cm及2 V寫入電壓下，不同側壁材料對於最佳化記憶體視窗的影響。研究發現鐵電電晶體在使用高介電係數側壁(k = 30)於面積比為1時，相比空氣側壁有較大的記憶體視窗;而在面積比為0.1時，使用空氣側壁的鐵電電晶體(k = 1)則比使用高介電係數側壁的鐵電電晶體有更大的記憶體視窗。鐵電電晶體在使用空氣側壁，其最佳化記憶體視窗為0.95 V。
論文最後使用殘餘極化為15 μC/cm^2、矯頑電場為1.2 MV/cm之鐵電電晶體，探討在低寫入電壓(2 V)下鐵電電晶體陣列受寫入干擾的影響，並分析受寫入干擾後的記憶體視窗。研究發現隨著面積比減小或是使用高介電係數側壁均能使寫入干擾的影響降低。考慮到使用高介電係數側壁會使電晶體的總電容增加進而降低操作速度，因此最後折衷的選擇是使用空氣側壁，並藉由減小面積比(AR)來降低寫入干擾的影響。我們將Si3N4側壁且AR = 1的鐵電電晶體做為我們比較的基準線，在考慮了寫入干擾後的記憶體視窗，使用空氣側壁的鐵電電晶體其最佳化記憶體視窗為0.74 V，相較於基準線的最佳化記憶體視窗為0.13 V，記憶體視窗有450%的改善。從以上結果可以知道減小面積比對於在低功耗的鐵電電晶體可以改善記憶體視窗(MW)，並且對於陣列的應用具有更好的抗寫入干擾能力。

關鍵字

鐵電電晶體 ； 低功耗 ； 記憶體視窗 ； 側壁 ； 寫入干擾

並列摘要

Ferroelectric field-effect transistors (FeFETs) are promising for emerging memory technologies, but reducing write voltage and increasing the memory window are vital challenges. Previous research suggests enhancing the memory window by connecting a ferroelectric capacitor with a MOSFET device, adjusting the area ratio of the ferroelectric layer to the MOSFET, and using high-k dielectric constant spacer materials. However, the optimization of the area ratio has rarely been examined. This thesis investigates the optimized area ratio (ferroelectric layer to MOS) to achieve the optimized memory window (MW) under various write voltages, ferroelectric parameters, and spacer materials. We use an equivalent capacitance model to explain the results. Finally, this thesis investigates the effects of different area ratios and spacer materials on write disturbance in FeFET arrays.
First, we investigated the relationship between the optimized area ratio (AR*) and the optimized memory window (MW*) of FeFETs with Si3N4 as the spacer material under different write voltages, remanent polarization (Pr), and coercive fields (Ec). We found that the optimized area ratio increases with the rise in write voltage. Additionally, we discovered that at a high write voltage (4.5 V), some ferroelectric parameters have an AR* = 1, indicating that reducing the area ratio does not necessarily increase the memory window. Through analysis of the impact of different ferroelectric parameters and area ratios on the optimized memory window of FeFETs, this research found that at a low write voltage of 2 V, FeFETs exhibit the largest optimized memory window of 0.89 V with a remanent polarization of 15 μC/cm² and a coercive field of 1.2 MV/cm.
This study further investigates how different spacer materials affect the optimized memory window of FeFET at a remanent polarization of 15 μC/cm², a coercive field of 1.2 MV/cm, and a write voltage of 2 V. We found that FeFET with high-k dielectric constant spacer (k = 30) have a larger memory window at AR = 1 compared to air spacer. However, at AR = 0.1, FeFET with air spacer (k = 1) shows a larger memory window. The optimized memory window for FeFET with air spacer is 0.95 V.
The study concludes by examining the impact of write disturbance on a FeFET array with a remanent polarization of 15 μC/cm², a coercive field of 1.2 MV/cm, and a write voltage of 2 V. We found that reducing the area ratio or using a high-k dielectric constant spacer can lessen the write disturbance. However, high-k dielectric spacer increases total capacitance and reduces speed, so the preferred solution is to use an air spacer and reduce AR. Compared to a baseline FeFET memory with Si3N4 spacer and AR = 1, the optimized memory window for FeFET with air spacer is 0.74 V, a 450% improvement over the baseline's 0.13 V. The results indicate that reducing AR can improve MW in low-power FeFETs and enhance immunity to write disturbances in array applications.

並列關鍵字

FeFET ； low-power ； memory window ； spacer ； write disturb

參考文獻

[1] M. Lapedus, “A new memory contender?” 2018. [Online]. Available: https:semiengineering.com/a-new-memory-contender/

[2] V. Milo, G. Malavena, C. M. Compagnoni and D. Ielmini, "Memristive and CMOS devices for neuromorphic computing", Materials, vol. 13, no. 1, pp. 166, Jan. 2020.

[3] T. Mikolajick et al., "Next generation ferroelectric materials for semiconductor process integration and their applications", J. Appl. Phys., vol. 129, no. 10, Mar. 2021.

[4] J. Müller et al., "Ferroelectric hafnium oxide based materials and devices: Assessment of current status and future prospects", ECS J. of Solid State Sci. and Tech., vol. 4, no. 5, pp. N30-N35, 2015.

[5] T. Mikolajick, U. Schroeder and S. Slesazeck, "The past the present and the future of ferroelectric memories", IEEE Trans. Electron Devices, vol. 67, no. 4, pp. 1434-1443, 2020.