考量極紫外光閃焰及自對準雙圖案微影技術之繞線

Flare-Aware Routing for EUVL with Self-Aligned Double Patterning

陳柏霖(Bo-Ling Chen)

指導教授 ： 張耀文

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2019年)

https://doi.org/10.6342/NTU201903350

摘要

自對準雙圖案微影技術被認定為最有可能應用在先進製程節點的技術之一；而極紫外光微影相較於193奈米光波微影提高了解析度。將自對準雙圖案微影技術與極紫外光微影結合能達成更高的圖案密度，並同時受益於以上技術的優點。然而極紫外光微影因其系統內反射性元件與反射性光罩的表面不平整性承受了閃焰效應；此效應會傷害關鍵尺寸的均勻性。同時，在雙圖案微影技術中，疊對誤差控制亦為影響圖案品質的關鍵因素。在本論文中，我們首先發展一演算法結合極紫外光微影與能提高設計彈性的自對準雙圖案微影技術搭配切除光罩。我們的演算法不僅能同時圓融的結合並處理兩個不同技術，更使得繞線步驟後續的虛擬電路填充更加容易，來進一步改善閃焰效應。作為實驗評估的基準，我們使用了先前研究的測試案例與自行合成的測試案例。實驗結果顯示相較於先前研究，我們的演算法能有效的減少疊對誤差長度以及形成較小的閃焰效應。

關鍵字

實體設計 ； 製造可行性設計 ； 極紫外光 ； 閃焰效應 ； 自對準雙圖案微影技術 ； 繞線

並列摘要

Self-aligned double patterning (SADP) is one of the most promising technologies for advanced nodes, while extreme ultraviolet lithography (EUVL) achieves a better resolution than the 193 nm ArF optical lithography system. EUVL combined with SADP can achieve higher patterning density and gain the benefits from both technologies. However, EUVL suffers from significant flare effects due to the surface roughness of its optical components and masks, which could harm the critical dimension (CD) uniformity. In contrast, the overlay control also causes critical issues for the pattern quality in the SADP technology. In this thesis, we first develop a routing algorithm combining the EUVL and the spacer-is-dielectric SADP using acut process which is popular for high design flexibility. Our algorithm can not only integrate the two objectives smoothly, but also make dummification easier in the post routing stage to further improve the flare effect.We evaluate our algorithm on the benchmark from the previous works and new synthesis ones. Experimental results show the effectiveness of our method with fewer overlay length and smaller flare effect compared to the previous work.

並列關鍵字

Physical Design ； Design for Manufacturability ； Extreme Ultraviolet Lithography ； Flare Effect ； Self-Aligned Double Patterning ； Routing

參考文獻

[1] R. K. Ali, A. H. Fatehy, N. Lafferty, and J. Word, "Ultimate patterning limits for EUV at 5nm node and beyond," in Proceedings of SPIE Advanced Lithography, vol. 10583, p. 1058321, San Jose, CA, February 2018.

[2] H. Aoyama, Y. Tanaka, K. Tawarayama, N. Nakamura, E. Soda, N. Oda, Y. Arisawa, T. Uno, T. Kamo, K. Matsunaga, D. Kawamura, T. Tanaka, H. Tanaka, S. Saito, and I. Mori, "Applicability of extreme ultraviolet lithography to fabrication of half pitch 35nm interconnects," in Proceedings of SPIE Advanced Lithography, vol. 7636, p. 76361N, San Jose, CA, February 2010.

[3] W. Arnold, M. Dusa, and J. Finders, "Manufacturing challenges in double patterning lithography," in Proceedings of IEEE International Symposium on Semiconductor Manufacturing, pp. 283--286, Tokyo, Japan, September 2006.

[4] G. E. Bailey, A. Tritchkov, J.-W. Park, L. Hong, V. Wiaux, E. Hendrickx, P. X. Staf Verhaegen, and J. Versluijs, "Double pattern EDA solutions for 32nm HP and beyond," in Proceedings of SPIE Advanced Lithography, vol. 6521, p. 65211K, San Jose, CA, February 2007.

[5] Y. Ban, K. Lucas, and D. Z. Pan, "Flexible 2D layout decomposition framework for spacer-type double pattering lithography," in Proceedings of ACM/IEEE Design Automation Conference, pp. 789--794, San Diego, CA, June 2011.