- 學位論文
探討單層二硫化鉬上閘極電晶體透過微縮等效氧化層厚度改善次臨界擺幅之研究
Investigate the Improvement of Subthreshold Swing in Monolayer MoS2 Top-Gate Transistors with Scaled EOT
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摘要
本論文主要探討藉由原子層沉積 (ALD) 生長高介電係數的介電層藉以微縮二硫化鉬電晶體的等效氧化層厚度 (EOT) 並且同時改善次臨界擺幅 (SS)，進一步提升閘極的控制能力。 第一部分為建立一個穩定生長High-k的ALD製程，主要為生長HfO2介電層，會先使用MIM平行板結構對不同生長溫度及厚度的生長參數做電容-電壓的量測來確認生長的品質，接著會先使用兩種介電層來製作以半金屬 (銻Sb) 作為接觸電極的全背閘極短通道 (Lch=50nm) 元件，一種為氮化矽基板100nm，另一種為ALD生長的HfO2介電層，我們利用HfO2微縮了等效氧化層厚度，使閘極控制能力提升進而降低了次臨界擺幅，同時也維持了和使用氮化矽基板一樣的高導通電流。 第二部分藉由更換上閘極的結構來進一步提升閘極的控制能力，為了著重於通道材料而減少接觸電阻的影響，我們先對長通道 (Lch=2µm) 的上閘極電晶體進行研究。其中我們透過0.7nm的鋁種子層成功改善了High-k經由ALD在二維材料上沉膜不均勻的問題，達到低漏電的要求 (<1x10-5 A/cm2)。同時間我們對其進行介電層的後退火，降低介面缺陷密度 (Dit) 改善了介電層的品質，次臨界擺幅約140 (mV/decade) ，提升了元件的開關效率。 第三部分為了解決HfO2在縮小厚度時介電常數下降造成EOT無法有效微縮的問題，而會對更高k值的介電層 (HZO) 進行探討，其更高的介電常數成功將EOT下降至1.2nm。 本研究使用ALD生長High-k材料於二硫化鉬電晶體中並結合後退火提升了元件的開關特性，製備出了低功耗、低 EOT的二硫化鉬上閘極電晶體。
並列摘要
In this thesis,we discusses the use of atomic layer deposition (ALD) to grow high dielectric constant (High-k) dielectric layers for scaling down the equivalent oxide thickness (EOT) of molybdenum disulfide (MoS2) field-effect transistors (FETs) while improving the subthreshold swing (SS) and enhancing the gate control capability. The first part involves establishing a stable ALD process for growing a High-k dielectric layer, primarily HfO2. Capacitance-Voltage measurements using a Metal-Insulator-Metal (MIM) parallel plate structure are performed to characterize the quality of the grown films at different growth temperatures and thicknesses. Subsequently, two dielectric layers, one with a 100nm silicon nitride substrate and the other with ALD-grown HfO2, are utilized to fabricate Global Back-Gate short channel (Lch=50nm) devices with a semimetal (Antimony, Sb) serving as the contact electrode. By scaling down the effective oxide thickness through HfO2 deposition, the gate control capability is enhanced, leading to reduced subthreshold swing while maintaining high on-state current similar to devices using a silicon nitride substrate. In the second part, we further enhanced the control capability of the gate by changing the structure of the Top-Gate. To reduce the impact of contact resistance and focus on the channel material, we conducted research on the Top-Gate transistor of a long-channel device (Lch=2µm). Through the implementation of a 0.7nm aluminum seed layer, we successfully addressed the issue of non-uniform deposition of High-k material on the two-dimensional surface using Atomic Layer Deposition (ALD), achieving the requirement for low leakage current (<1x10-5 A/cm2). At the same time, we performed post-annealing of the dielectric layer to reduce the interface defect density (Dit) and improve the quality of the dielectric layer. The subthreshold swing was approximately 140 (mV/decade), leading to an improvement in the switching efficiency of the device. In the third part, to overcome the problem of ineffective EOT scaling due to the decrease in dielectric constant when reducing the thickness of HfO2 , we investigate dielectric layers with higher dielectric constants (HZO). Due to its higher dielectric constant, the EOT is successfully reduced to 1.2nm. This study utilizes ALD to grow High-k materials in molybdenum disulfide transistors and combines post-annealing to enhance the device's switching characteristics, resulting in low-power, low EOT molybdenum disulfide FETs.
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