摘要
隨著製程技術的進步，對於氧化層的各種不同特性要求也越嚴苛。當氧化層變得越薄，在反轉層時，原本只受電場加速的載子不再被我們的絕緣層阻擋住而直接穿透過去，因此形成相當大的穿隧電流。在做成元件之後，便無法達到低必v消耗的要求。本論文中，就是以原子層化學汽相沉積的高介電係數的材料來取代二氧化矽。利用高介電係數的材料作為絕緣層時，就能以更大的厚度降低載子直接穿透的機率，而使大部份的電荷維持在表層。 因為在原子層化學汽相沉積的成長過程中，會殘留水汽在我們使用的高介電係數的材料，並且因過度的氯氣而在介電層中產生缺陷。所以在成長完成之後，我們會針對這個問題用快速退火的方式解決，以免影響到元件本身的電性。藉由穿透式電子顯微鏡觀察到，預先以化學反應成長的二氧化矽阻擋層，在經過更高溫度，更長時間的退火處理，有繼續增加的趨勢。可以得知，外界多餘的氧仍能在高溫的情況下，鑽過絕緣層，和底部的矽反應形成二氧化矽。所以目前我們所能達到的等效二氧化矽絕緣層厚度大約為1.5個奈米。 然而，在我們使用的高介電係數的材料在以600度以上的高溫處理過後，不只厚度變高，並且會形成以多晶體的狀態存在。由於多晶體彼此互相連接的結晶邊界變得更多，使得載子能經由這些結晶邊界產生路徑，穿越絕緣層，形成更大的電流.。 另一方面，本材料直接和矽接合時，產生的界面缺陷,比二氧化矽更為嚴重。如何解決這些問題，便是我們當前努力的目標.。
並列摘要
The various electrical and material properties of dielectrics are even more important along with the progress of our process technology. When thickness of oxide becomes very thin, carriers which can only be accelerated by electric field in inversion are no longer confined by the insulator and they will easily penetrate through the insulator to form a large number of leakage currents. The goal to low power consumption couldn’t be achieved and those devices are barely adopted. In this thesis, the alternative high-k dielectrics made by atomic layer chemical vapor deposition are used to instead of silicon dioxide. Therefore, the probability of carries directly penetrating through the insulator will be reduced with thick high-k film, and then charges can be kept in surfaces. The residual water was left in those deposited films and defects within insulators were formed due to overall chlorine during the process of atomic layer deposition. The problems could be eliminated by rapid thermal annealing after the deposition in order to enhance the good electrical characteristics of those films. According to the photography from transmission electron microscopy, we find that the intentionally grown chemical oxide became thicker after high temperature and long time annealing. It shown that the residual oxygen in the chamber penetrated through the high-k film and reacted with silicon to form silicon dioxide. The best we can do so far is to deposit high-k film with EOT below 1.5nm. However, all the high-k films were all crystallized after annealing at 600OC. This resulted in the increase of leakage currents. On the other hand, the interface trap charges with high-k dielectrics are larger than those with silicon dioxide. We will do our best to solve these problems.