摘要
隨機處理器主要著重在處理不確定性的錯誤，系統的穩定性(抗錯誤能力)是最重要的設計考量。執行作業系統的處理器，是不容許發生的錯誤。為了要達到無錯誤的目的，使用具有抵抗錯誤能力的電路是必需的。除了穩定性之外，記憶體系統的效能是另外一個不可忽視的設計考量。為了要使記憶體系統可以跟上處理器的速度，第一階層高速緩存控制器扮演非常重要的腳色。假設一個高效能的管線式處理器所具有的高速緩存記憶體系統容量是固定的，則減少失效代價似乎是一個能夠進一步增加處理器效能的方法。 本論文中，將詳細介紹應用在ARM1136JF-S隨機處理器內之記憶體管理系統的實作。記憶體管理系統包括記憶體管理單元、具有Outstanding Critical Word First Buffering (OCWFB)機制的第一階層高速緩存控制器、系統協同處理器以及、隨機協同處理器。OCWFB¬機制是將本論文所提出的一個演算法實踐於第一階層高速緩存控制器，以便隱藏第一階層高速緩存失效所造成的處理器停擺。從處理器停擺的角度去衡量效能，此機制可以提升大約40%的效能。隨機協同處理器是此論文所提出具有時序偵測和錯誤復原機制，總共靠兩個電路來完成電路的保護：一個週期性時序偵測電路，能夠感測環境變異以提升Razor的錯誤的抵抗能力；一個路徑追蹤與時序檢查電路，能夠追蹤第一階層高速緩存以及記憶體管理單元的信號路徑，確保沒有任何時序上的錯誤會發生。
並列摘要
Stochastic processors are designed to handle non-deterministic errors. The robustness issue is the most important design consideration. No error is allowed in an OS-based processor. To achieve an error-free processor, error-resilience circuits are necessary. In addition to the robustness issue, the performance of a memory system is another crucial design consideration. Level-one Cache Controller plays an important role to make the memory system keep up with the high frequency of the processor. Given a high-performance pipeline processor and a cache memory capacity limitation, reducing miss penalty seems to be a possible solution to further enhance the performance of the processor. In this work, implementation of a Memory Management System for a Stochastic ARM1136JF-S is elaborated in details. This Memory Management System includes a Memory Management Unit (MMU), a Level-one Cache Controller (L1 Cache Controller) with an Outstanding Critical Word First Buffering (OCWFB) mechanism, a System Coprocessor, and a Stochastic Coprocessor. A proposed OCWFB mechanism is implemented in the L1 Cache Controller to hide the CPU stalls caused by the L1 Cache Miss. In terms of CPU stalls, the performance reaches approximately 40% improvement. The Stochastic Coprocessor is a proposed coprocessor with a timing detection and a recovery mechanism inside. This coprocessor consists of two circuits: a cycle-based timing-detection circuit capable of detecting the environmental variations to enhance the error-resilience ability of Razor and a path-tracing timing-checking circuit capable of tracing the circuit path of L1 Cache and MMU to ensure no timing errors.
參考文獻
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