- 學位論文
CRC:低峰值功率可測試技術設計
Complemented Response Cell (CRC) : A Low Peak Power design for Testability Technique
摘要
本論文提出一個低峰值功率可測試技術，其名稱為互補式輸出資料單元，主要是可降低在系統時脈時的峰值功率。此技術控制掃瞄鍊上特定的幾個掃瞄單元，使他們在系統時脈前後保持不變。在此技術中還提出一個計分的方法，其目地是用來選擇掃瞄鍊上特定的掃瞄單元並且將他們用互補式輸出資料單元置換。此技術跟已發展的低功率可測試設計最大的不同點在於此技術只要更動原來設計非常少的部分就可以達到不錯的效果。在ISCAS'89基準電路的實驗顯示，此技術可以將S38417的峰值功率降低57%。 此技術的特色在於即不需要額外的控制訊號也不需要增加額外的繞線，此外，此技術不會降低錯誤覆蓋率而且增加的面積相對很小。
並列摘要
This thesis presents a novel low peak power DFT technique, called Complemented Response Cell (CRC), to reduce the peak power at the system clock. This technique controls the data input of specified scan cells such that their contents remain unchanged before and after the system clock. A scoring method is proposed to select only a small number of scan cells replaced by CRC. The proposed technique is very different from the pervious technique is that it requires minimum change in the existing MUX-scan design for testability (DFT) methodology. According to the experimental data on ISCAS’89 benchmark circuits, the CRC technique reduces the peak power by up to 57% (S38417). In the CRC technique, neither extra control signal nor extra routing of scan chain is needed. Besides, there is no fault coverage loss and the area penalty is very small.