案例研究:軟體自我測試應用於8051微控制器

Software-Based Self-Test: Case Study on 8051

劉邦佐(Bang-Zuo Liu)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電機工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202200637

摘要

軟體自我測試(Software-Based Self-Test)具有在線測試與功能模式下測試的優點，又由於近幾年來，生命安全攸關的產品和汽車電子產品的高度發展，軟體自我測試作為產品出廠後仍然可以進行自我測試的方法，受到了更多關注。
在本論文中，我們將軟體自我測試方法應用到了微控制晶片8051上，並且克服了遇到的困難，成功在不同電路架構上實現軟體自我測試。
在研究過程中，我們得知面對不同的架構所需要使用的模板(template)將會非常不同，因此我們更加嚴格的進行功能約束(functional constraint)以提高軟體自我測試方法的可行度，並為了更有效的進行自我測試方法以及減少時間成本，我們提供了針對暫存器檔案(register file)的故障先行測試的策略。從對8051進行軟體自我測試的結果可以看到，我們所提出的軟體自我測試方法可以實現79.22%的轉換延遲故障(transition delay fault)測試覆蓋率。
通過這些研究，我們可以更清楚的知道在不同架構的待測電路中，使用軟體自我測試方法可能會遭遇的問題，以及哪些電路設計架構會更適合使用軟體自我測試方法的實踐。人們將能更快速地找出適用待測電路的新模板。

關鍵字

軟體自我測試 ； OC8051 ； 測試模板 ； 功能約束 ； 轉態延遲錯誤 ； 超大積體電路測試

並列摘要

Software-Based Self-Test (SBST) has the advantages of on-line testing in functional mode, and due to the high development of life-safety-critical products and automotive electronic products in recent years. SBST has received more attention as a method for self-testing after products leave the factory.
In this paper, we apply SBST method on 8051 microcontroller, and overcome the problem of replacing the circuit under test, and successfully implement SBST on different circuit architectures.
During these researches, we learned that the templates used for different architectures can be very different, so we make stricter functional constraints to improve the feasibility of SBST methods. Furthermore, we provide a testing strategy for the register file faults, which is more efficient and shorten time cost. From the experimental results of SBST on 8051, it shows that our proposed SBST method can achieve 79.22% transition delay fault coverage.
Through these studies, we can see the problems encountered by different architectures of the design under test using SBST method more clearly, and know which architecture is more suitable for the using SBST method. People will be able to find new templates more quickly for the design under test.

並列關鍵字

Software-Based Self-Test ； OC8051 ； Test Template ； Functional Constraint ； Transition Delay Fault ； VLSI Testing

參考文獻

[1] Mihalis Psarakis, Dimitris Gizopoulos, Ernesto Sanchez, and Matteo Sonza Reorda. Microprocessor software-based self-testing. IEEE Design Test of Computers, 27(3):4–19, 2010.

[2] Nasim Zeinolabedini. Average-case analysis of power consumption in embedded systems. PhD thesis, University College Cork, 2015.

[3] Paolo Bernardi, Riccardo Cantoro, L Ciganda, Ernesto Sánchez, M Sonza Reorda, Sergio De Luca, Renato Meregalli, and Alessandro Sansonetti. On the in-field functional testing of decode units in pipelined risc processors. In 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pages 299–304. IEEE, 2014.

[4] Kazuko Kambe, Michiko Inoue, and Hideo Fujiwara. Efficient template generation for instruction-based self-test of processor cores. In 13th Asian Test Symposium, pages 152–157. IEEE, 2004.

[5] Nihar Hage, Rohini Gulve, Masahiro Fujita, and Virendra Singh. On testing of superscalar processors in functional mode for delay faults. In 2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID), pages 397–402. IEEE, 2017.