- 學位論文
應用於USB3之資料時脈回復電路
A Clock and Data Recovery Circuit applied for USB3
摘要
本論文以55奈米互補式金屬氧化半導體製程實現具有符合USB3速率10Gb/s、5Gb/s 並支援 Display port 速率 8.1Gb/s、5.4Gb/s、2.7Gb/s、1.62Gb/s 之資料時脈回復電路。電路包含連續時間線性均衡器、可調增益放大器、相位偵測器、頻率偵測器、鎖定偵測器、自適應延遲校正電路、電壓控制震盪器、頻率選擇電路、帶隙參考電壓電路、1 對32 解碼器組成一資料時脈回復電路。量測上在 10Gb/s、5.4Gb/s、5Gb/s、2.7Gb/s 速率下位元錯誤偵測器驗證皆為真，功率消耗為 516mW，8.1Gb/s 與 1.62Gb/s 因為電壓控制震盪器頻率飄移無法驗證。
並列摘要
This thesis presents a clock data recovery circuit that supports USB3 and Display port data rate 10Gb/s, 5Gb/s, 8.1Gb/s, 5.4Gb/s, 2.7Gb/s, 1.62Gb/s. The circuit includes continuous-time linear equalization (CTLE), variable gain amplifier (VGA), phase detector, frequency detector, lock detector, delay calibration, voltage-controlled oscillator (VCO), and VCO frequency band selector, bandgap reference, and 1-to-32 demultiplexer (DEMUX). In the measurement, bit error rate test at 10Gb/s, 5.4Gb/s, 5Gb/s, 2.7Gb/s is error-free. Bit error rate test at 8.1Gb/s and 1.62Gb/s failed because the VCO frequency is not covered 8.1GHz.