- 學位論文
矽穿孔及先進元件自發熱效應之模擬分析
Simulation of Through Silicon Via and Self-heating Effects on Advanced Devices
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摘要
跟隨著摩爾定律，半導體元件持續微縮，製程技術同時也面臨了瓶頸，當傳統的矽金氧半電晶體無法再依尺寸比例持續縮小時，除了改變電晶體的結構形狀，以鰭式場效電晶體取代了平面式電晶體來維持定律的成長速率外，晶片以三維的方式堆疊也被提出，不同於過去晶片設計的結合方式，透過晶片的垂直堆疊，以三維的封裝技術取代傳統二維的打線接合，不僅使得導線傳遞路徑縮短，有更快的傳輸速度和更少的功率消耗，同時也增加了晶片的密度以延續摩爾定律的極限，而矽穿孔正是其中的關鍵技術。此外，隨著極度微縮的元件密度增加，代表著很小的面積裡會有更多的電晶體在操作著，這將產生更為嚴重的熱效應，這會影響元件表現並造成可靠度的問題，進而增加電路設計的困難，因此，元件的散熱問題變得十分重要且需要被解決。 本論文的主軸主要分為兩個主題，其一是針對矽穿孔的熱應力分佈進行分析和討論，另外是研究先進元件的自發熱效應及散熱問題，這都是在半導體技術應用上正在發生的問題。首先，我們利用模擬軟體分析矽穿孔對於周圍矽基板區域產生的熱應力，並探討在陣列中相鄰矽穿孔之間應力的交互作用。此外，我們也提出藉由改變材料特性之模型以符合實際元件之應變表現。除了應力分析外，討論應力可能對周圍元件電流的影響也是很重要的一環，利用數學理論和實際實驗的量測結果互相驗證我們建立出一不對稱的隔離區模型，可作為電路設計之參考。關於第二個主題則是討論先進元件的自發熱效應，我們利用模擬軟體架構出鰭式場效電晶體，對其自發熱效應進行分析，探討在先進製程裡三維電晶體熱傳導及溫度分布，考慮元件周圍結構之熱傳導差異以預測電晶體之最高溫度和熱傳導路徑。
並列摘要
Moore’s Law is the main driving force in the semiconductor industry, the number of transistors in the integrated circuit has doubled almost every two years. However, it is becoming more challenging for the semiconductor manufacturing technology to follow the trend as in the past. While the conventional MOSFETs face the scaling limits, 3D transistors such as FinFETs improve the transistor feature size and performance over planar MOSFETs to continue the scaling trend. However, the increasing device density, materials with poor thermal conductivity and the physical confinement of the device geometries are responsible for the increased the self-heating effects in ultra-scaled transistors. Instead of the reduction of the transistor size, 3D IC has also been demonstrated as a feasible technology. While traditional methods of interconnect such as wire bonding need long cross-chip interconnects, 3D ICs achieve shorter interconnect architectures by stacking one die on top of another dies. 3D packaging technology offer an alternative that not only improve the overall transmission speed and reduce the power consumption, but also increase the functionality of ICs at a smaller footprint. In this way, it extends the semiconductor scaling limits beyond the roadmap predicted by Moore's. Law, and TSV is one of these key technologies as an effective solution. The content of the thesis can be divided into two major parts. First, we discuss about the effect of thermo-mechanical stress induced by TSV structures. We simulated the thermo-mechanical stresses near the surface of Si substrate and investigate its impacts on the performance of the nearby electronic devices. With the experimental results and numerical calibrations, we present a keep out zone model. Second, the self-heating effects on advanced devices and the heat dissipation have been investigated. Self-heating effects can not only degrade device performance but also accelerate degradation mechanism, and all these problems may increase the difficulty in IC designing. Therefore, the thermal issue becomes very important and needs to be solved and we are trying to study the self-heating effects on advanced devices.
參考文獻
[1] Wu, Shien-Yang, et al. "An enhanced 16nm CMOS technology featuring 2 nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications." Electron Devices Meeting (IEDM), 2014 IEEE International. IEEE, 2014.
[2] S. Natarajan, et al. "A 14nm Logic Technology Featuring 2nd-Generation FinFET Transistor, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 m2 SRAM cell size," International Electron Devices Meeting (IEDM), 2014.
[3] J. C. Lin, et al. “High density 3D integration using CMOS foundry technologies for 28 nm node and beyond,” in IEDM Tech. Dig., 2010, pp. 22–25.
[4] H. Chaabouni, et al. “Investigation on TSV impact on 65nm CMOS devices and circuits,” in IEDM Tech. Dig., 2010, pp. 796–799.
[5] A. Mercha et al, "Impact of thinning and TSV proximity on high-k/metal gate first CMOS performance," Proc of the IEEE VLSI Technology Conference p 109, 2010.