- 學位論文
利用四端量測分析單閘極與雙閘極氧化亞錫薄膜電晶體之電性
Characterization of P-Type Single-Gate and Double-Gate Tin Monoxide Thin-Film Transistors Using Gated-Four-Probe Measurements
摘要
本研究在玻璃基板上開發單閘極與雙閘極氧化亞錫薄膜電晶體，並利用四端(gated-four probe)量測分析其電性。首先，透過主動層厚度的調變以及主動層後退火處理，成功提升單閘極氧化亞錫薄膜電晶體之載子遷移率。接著，透過四端量測對主動層的本質電性以及接觸電阻進行探討，並將最佳化之製程參數應用到雙閘極薄膜電晶體製作上，並針對上閘極材料以及操作模式對元件特性影響進行分析，最終利用上閘極有效調控臨界電壓。 實驗中利用射頻磁控濺鍍系統在室溫下，透過金屬錫靶材製備厚度分別為15、17.5和20 nm的氧化亞錫薄膜，接著在空氣環境下進行225℃退火0.5、1、2、3和5分鐘。由低掠角X光繞射頻譜發現氧化亞錫薄膜厚度17.5 nm搭配退火3分鐘條件下，具最顯著(101)晶相。而在成分分析上，X光光電子能譜分析顯示隨著退火時間的增長，薄膜中金屬錫Sn0+的比例隨之下降，四價錫Sn4+的比例隨之上升。在相同退火時間下，較薄之薄膜成分較偏向四價錫Sn4+，而較厚的薄膜則較偏向金屬錫Sn0+。 在下閘極結構之薄膜電晶體電性方面，當主動層厚度為17.5 nm時，隨著退火時間的增加非本質(即場效)載子遷移率會先增而後減，最高非本質載子遷移率發生在退火條件為3分鐘，達2.65 cm2/V∙s，此與其結晶性與成分比例有明顯相關性。研究中也觀察到隨著主動層厚度增加，其達到最佳非本質載子遷移率的退火時間亦漸增，例如主動層厚度為15 nm時，最佳非本質載子遷移率發生在退火時間為2分鐘的條件下，達到1.64 cm2/V∙s；而厚度為20 nm時，則在退火時間為5分鐘時達到最佳非本質載子遷移率的2.06 cm2/V∙s。此外，我們透過四端量測分析其薄膜電晶體之本質載子遷移率、通道本質電阻以及接觸電阻，發現在最佳條件下(厚度17.5 nm、退火3分鐘)擁有最低的通道本質電阻及接觸電阻。而當非本質載子遷移率越高時，所量測出來的本質載子遷移率也會越高，且兩者間的差異與接觸電阻相關，同時較高的接觸電阻亦伴隨著最低的載子遷移率。 最後我們將具最佳化之主動層製程參數(厚度17.5 nm、退火3分鐘)的下閘極氧化亞錫薄膜電晶體應用至雙閘極薄膜電晶體上。結果發現，使用功函數較小的上閘極材料，能降低電晶體臨界電壓之絕對值，故在操作模式研究中採用金屬鈦為上閘極材料。當上閘極施加偏壓由 0 V增加至4 V時，以下閘極操作薄膜電晶體，臨界電壓可由2.13 V降低至 0.83 V；而在雙閘極同時操作的情形下，能夠使其開電流提升，且其電流開關比達四個數量級。此雙閘極結構能夠藉由不同的操作模式調變薄膜電晶體臨界電壓並提升其電性。
並列摘要
In the research, we demonstrated single-gate and double-gate tin monoxide (SnO) thin film transistors (TFTs), and characterized the electrical performance by gated-four probe measurement. First, we investigated the effect of thickness and annealing time of the SnO channel on the electrical performance of single-gate TFTs. Gate-four probe measurements were carried out to evaluate the channel resistance and contact resistance. Next, the optimal condition obtained is applied to the double-gate SnO TFTs. The influence of the top-gate material and the operation mode on the electrical characteristics of double-gate TFTs was studied. SnO thin films of 15, 17.and 20 nm were deposited by reactive rf-sputtering at room temperature using a metal tin target, followed by an annealing process at 225℃ in air ambient for 0.5, 1, 2, 3 and 5 min. The glancing-angle X-ray diffraction spectra show that the 17.5 nm SnO film with an annealing time of 3 min exhibits the strongest (101) diffraction peak among all. The X-ray photoelectron spectroscopy analysis shows that as the annealing time of the SnO thin film increases the amount of metallic Sn decreases and the amount of Sn4+ increases. For the same annealing time, the thinner film contains more Sn4+ and the thicker film has more metallic Sn. For the bottom-gate SnO TFT with 17.5 nm-thick channel layer, the extrinsic (linear field-effect) mobility increases first and then decreases as the annealing time increases. The optimal extrinsic mobility reached 2.65 cm2/V∙s when the annealing time is 3 min. The electrical performance is highly dependent on the crystalline phase and content of the SnO channel. In addition, as the thickness of the SnO channel layer increases, the optimal annealing time increases. For instance, the optimal annealing times for the 15-nm-thick and 20-nm-thick SnO channel layers are 2 and 5 min, respectively, and the corresponding linear mobilities achieved are 1.64 and 2.06 cm2/V∙s. The intrinsic mobility, intrinsic channel resistance and contact resistance were analyzed by gated-four probe measurements. We found that the lowest channel resistance and the contact resistance was obtained in the optimal condition. Besides, when the extrinsic mobility is higher, the higher intrinsic mobility can be measured. The difference between extrinsic and intrinsic mobility is correlated with contact resistance. In the meantime, the lower contact resistance is, the higher mobility of TFT can be. Finally, the optimal condition of bottom-gate SnO TFT obtained is then applied to the double-gate SnO TFT. By using different top-gate metal material, the threshold voltage of the bottom-gate mode can be modulated. The lower the work function of top metal gate, the smaller the threshold voltage. Therefore, Ti is chosen as the top gate material for the subsequent experiments. As the bias voltage of the top gate increases from 0 to +4 V, the threshold voltage of the bottom-gate mode decreases from 2.13 V to 0.83 V. In the dual-gate operation mode, on-current were enhanced and on/off ratio of > 104 were obtained. The results show that the threshold voltage can be modulated and the electrical performance can be improved by using a double-gate architecture.