機器學習式功能約束提取應用於軟體自我測試

Machine Learning Based Functional Constraint Extraction for Software-Based Self-Testing

林啟源(Chi-Yuan Lin)

指導教授 ： 黃俊郎

國立臺灣大學/電機資訊學院/電子工程學研究所/碩士(2020年)

https://doi.org/10.6342/NTU202003852

摘要

軟體自我測試（Software-Based Self-Testing）是一種非侵入性、功能性以及全速測試的電路測試方式。與掃描式內建自我測試（Scan-based Built-In Self-Testing）相比，軟體自我測試是在電路的一般運行模式下進行測試，無須額外硬體設計即可用以測試電路，因此能減少設計測試電路所需之時間和製造成本。為了偵測現今CPU設計中由於工作頻率增加而可能導致的延遲錯誤（Timing violation），本文針對處理器的轉態延遲錯誤（TDF）提出了一種基於機器學習技術的新穎方法，用於較短的時間內提取處理器行為，藉此產生約束來限制自動測試圖樣產生系統（ATPG）生成更近乎功能性的測試圖樣，這些測試圖樣將被應用於增強式學習（RL）的測試程序生成器。
由於處理器設計的複雜性可能導致增強式機器學習性能降低，因此我們提取功能約束以減少其搜索空間。在本文中，我們的方法將應用於MIPS32架構，旨在檢測轉態延遲錯誤。結果顯示，故障激活率可提高約10%，故障覆蓋率大約可提高20%，增強式學習的訓練時間可減少約80%。

關鍵字

應用軟體自我測試 ； 轉態延遲錯誤 ； 增強式學習 ； 測試程序生成 ； 功能性約束提取

並列摘要

Software-based self-test (SBST) is a non-invasive, functional, and at-speed circuit testing method. Compared with scan-based Built-In Self-Test (BIST), SBST operates in normal operating mode and can test the circuit without additional hardware design. Therefore, the design time and manufacturing cost can be reduced.
To detect the delay faults caused by the increasing operating frequency in modern CPU designs, the proposed work uses learning techniques to target the processor's transition delay faults (TDF). A novel high-level simulation method is proposed for extracting the processor behavior in a shorter time and helping constrain the ATPG for generating more functional test patterns. These test patterns are the target states for the reinforcement learning (RL) based test program generation. With the growing CPU complexity, generating instruction sequences to reach these target states becomes challenging, incurring long model training time for the RL-based test program generator. The proposed constraint extraction technique addresses this issue by pruning the search space. This significantly reduces the model construction complexity and leads to more stable outcomes.
To validate the proposed technique, we apply the proposed constraint extraction technique to a MIPS32 CPU, targeting transition delay faults. The results show 10% improvement in fault activation rate, approximately 20% improvement in fault activation and 80% reduction in RL modeling training time.

並列關鍵字

Software-Based Self-Testing ； Transition Delay Fault ； Reinforcement Learning ； Test Program Generation ； CPU Functional Constraint Extraction

參考文獻

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