基於二維向量圖之點陣化FPGA加速器

FPGA-Based Accelerator of Two-Dimensional Vector Image Rasterization

徐觀(Kuan Hsu)

指導教授 ： 陳昭宏

國立臺灣大學/工學院/工程科學及海洋工程學研究所/碩士(2022年)

https://doi.org/10.6342/NTU202202521

摘要

隨著電子產業愈加發達及完整，人們的生活智慧化，未來產品的需求也必定會高速變化。面對快速變化的產品需求，現有的傳統光罩製程開發新產品所耗的時程長，較無法進行快速對應，為此，可提供快速、彈性且也具備高精度生產的無光罩製程技術成為新興的科技產業核心。
本論文參與的計畫核心，數位微影技術(Digital Lithography Technology, DLT)，即為無光罩曝光技術之一，而本論文的研究為此技術中所需的Field-Programmable Gate Array (FPGA)韌體控制，嘗試將向量圖點陣化技術移植至FPGA板上，以FPGA板作為運算和傳輸核心。
為使即時的二維向量圖點陣化系統能達到計畫的速度需求，針對一部分的渲染程序進行硬體實現和加速，與起初軟體端的運算速度相比，硬體實現過後的渲染程序加速了至少十倍。

關鍵字

點陣化 ； 數位微影 ； 硬體加速 ； FPGA

並列摘要

With the prosperity of the electronics industry and people's lives getting more intelligent, the product demands will be sure to undergo rapid changes. To deal with the rapid changes in product demands, maskless lithography, which has the ability to provide fast, elastic and high precision fabrication has become an attractive solution for the lithography industry.
Digital Lithography Technology (DLT) is a kind of maskless lithography technology. The research for this thesis is a part of DLT, which copes with the control of Field-Programmable Gate Array (FPGA) and tries to move the rasterization of vector graphics onto an FPGA board.
To reach the performance demand of 1920x1080 1-bit resolution and 10k frames per second, this research involves hardware implementation and acceleration for a part of the rendering process in the rasterization of vector graphics. Compared to a pure software implementation, the rendering process on hardware is more than 10 times faster.

並列關鍵字

Digital Lithography ； Maskless Lithography ； FPGA ； rasterization ； hardware acceleration

參考文獻

[1] Texas Instruments, DLP6500 0.65 1080p MVSP Type A DMD datasheet (Rev. A), 2016

[2] Navarro Torrentó, A. (2015). Implementation of a GPU rasterization stage on a FPGA (Bachelor's thesis, Universitat Politècnica de Catalunya).

[3] Nadeau, E., Whorton, S. (2010). FPGA-Based Graphics Acceleration. Worcester Polytechnic Institute.

[4] Ucamco, The Gerber Layer Format Specification, 2022

[5] X. Wang, F. Guo and M. Zhu, "A more efficient triangle rasterization algorithm implemented in FPGA," 2012 Int. Conf. Audio Lang. Image Process., 2012, pp. 1108-1113, doi: 10.1109/ICALIP.2012.6376782.