並列摘要
The data is disturbed by any kind of noise during the transmission. In order to process the data synchronously and to purify it for the following circuits, clock and data recovery (CDR) circuit is adopted. In chapter 3 of this thesis, a 1-Gb/s full-rate CDR circuit with dual loops is fabricated in TSMC 0.18um 1P6M CMOS technology. Employing the frequency detector not only expands the operating frequency range but also speeds the locking process up. In chapter 4, a transceiver for intra-body communication (IBC) is implemented in TSMC 0.35um 2P4M CMOS technology. The transmitter directly transmits digital signal to the human skin, and the receiver based on CDR recovers the signal.
參考文獻
[1] Behzad Razavi, Design of Integrated Circuits for Optical Communications, 2003, McGraw-Hill, ISBN 0-07-282258-9.
[2] David A. Johns, Ken Martin, “Analog Integrated Circuit Design”, 1997.
[4] C. R. Hogge, “A Self-Correcting Clock Recovery Circuit,” IEEE J. Lightwave Tech., vol.3, pp. 1312-1314, Dec. 1985.
[5] B. Stilling, “Bit Rate and Protocol Independent Clock and Data Recovery,” Electronics Letters, vol.36, pp. 824-825, Apr.2000.
[6] W. Rhee, “Design of High-Performance CMOS Charge Pump in Phase-Locked Loops,” in Proc. 1999 IEEE International Symposium on Circuits and Systems, June 1999, pp.545-548.