在本論文中,我們提出了一個考慮多重邊界與操作模式之靜態時序分析引擎。它能在不同的大電路中有效率地計算出許多製程邊界中最大的延遲。我們關鍵的貢獻在於:(一)路徑模式與參數模式的縝密結合,使得此引擎在不同的電路下都是很健全的。(二)增強的搜尋空間刪除技巧。(三)簡易而有效率地計算出關鍵路徑延遲界限,大大地加強了起始搜尋空間刪除的能力。(四)延伸到保持時間的確認。我們的實驗結果顯示出在不同參數數量與不同電路下,我們的引擎都比以往的考慮多重編界與操作模式之靜態時序分析方法還要傑出。
In this thesis, we proposed a unified Multi-Corner Multi-Mode (MCMM) static timing analysis (STA) engine that can efficiently compute the worst-case delay of the process corners in various very large scaled circuits. Our key contributions include: (1) a seamless integration of the path- and parameter-based branch-and-bound algorithms so that the engine is very robust for different kinds of circuits, (2) an improved search space pruning technique, (3) a simple yet efficient critical path delay bound for the initial search space pruning, and (4) an extension to the hold-time check. Our experimental results show that our engine can significantly outperform the prior MCMM STA approaches in various benchmark circuits with different number of process parameters.