本論文主要內容是針對多層板電源接地平面所造成的電磁干擾問題做探討。在高速數位電路中,由於許多訊號線穿層或跨槽線的情況引發接地彈跳雜訊,使電磁波在層板間來回傳播與反射,並於邊緣產生電磁輻射雜訊,即電磁干擾。本文使用空腔共振器模型與共模�差模模態輻射模型解釋多層板輻射機制,並推導出一估算兩模態輻射量差值,即最大功率抑制輻射量。為了有效抑制多層板邊緣等效磁流所造成的電磁輻射問題,本文提出利用不同接地連通柱擺放方式,如一圈連通柱擺放、兩圈連通柱平行擺放以及兩圈連通柱交錯擺放方式,比較其抑制差模模態輻射的效果,並透過解析方法,分析如何使用最低成本擺放接地連通柱達到最佳輻射抑制效果。對於一圈連通柱擺放設計,其可抑制到40dB的EMI輻射量;而兩圈接地連通柱擺放可抑制到66dB以上的EMI輻射量。最後,利用電磁模擬軟體與GHz橫向電磁波傳輸室量測驗證此設計的準確性。
This thesis focuses on the problem of Electromagnetic Interference(EMI)of Printed Circuit Board(PCB)power/ground planes, which is a crucial issue to the whole system stability in high speed digital circuit. The primary noise of power/ground planes which arises from current flowing through a via or the signal trace crossing slot lines is the ground bounce. The electromagnetic waves reflecting back and forth from edges of the substrate generate a standing wave, which gives rise to radiated emission, and is often identified as EMI. The cavity resonator model together with a new even/odd mode radiation model is proposed to explain the radiated emission mechanism. The maximum power suppression between even and odd mode radiation is derived. This thesis then employs one way of using the shorting vias to suppress the odd mode radiation resulting from the PCB edges. By analytical methods, several designing methods of shorting vias placement, including 1-column vias, 2-column parallel vias and 2-column interlacing vias are presented. EMI suppression is above 40dB and 66dB for 1-column and 2-column vias design respectively. Finally, EM simulation tool “HFSS” and GTEM Cell measurement are used to validate the accuracy of the design.