- 學位論文
應用於高速有線通訊之時脈與資料回復架構
Clock and Data Recovery Architecture for High-speed Wire-line Communications
摘要
為了實現應用於高速有線通訊的時脈與資料回復電路，本論文首先提出一個具有頻率自動鎖定的半速率時脈與資料回復電路，電路透過相位內插電路產生所需的相位輸出，並在不使用環形振盪器的情形下，完成半速率頻率誤差偵測。電路以90nm CMOS的製程製作，其晶片面積為0.96×0.84mm2。在輸入10.3125Gb/s 27-1的擬似隨機位元序資料下，量測到的時脈峰對峰抖動與方均根抖動分別為14.54ps,pp與1.90ps,rms。在相同的輸入資料下，量測到的資料峰對峰抖動與方均根抖動分別為26.85ps,pp與5.12 ps,rms。在工作電壓1.2V的情況下，功率消耗為244mW，而抖動容忍度可超過IEEE 802.3ba的抖動容忍遮罩0.46UIpp。 雖然已完成單一通道的時脈與資料回復電路，但是在IEEE 802.3ba的實體層架構中，資料傳輸是以四個通道的方式進行。為了節省功耗、硬體成本和避免多組振盪器之間的干擾。本論文提出了結合一個時脈與資料回復電路與三組延遲鎖定迴路電路的多通道時脈與資料回復架構，時脈與資料回復電路提供I/Q時脈給延遲鎖定迴路使用，完成多通道時脈與資料回復。然而半速率非線性時脈與資料回復電路的輸出抖動過大，無法提供可靠的時脈輸出給延遲鎖定迴路使用。因此本論文接著提出混合式的相位誤差偵測電路，讓線性時脈與資料回復電路可以應用在高速操作。在考量下線硬體成本的情況下，我們選擇實現2×10Gb/s的多通道時脈與資料回復電路。此多通道時脈與資料回復電路以90nm CMOS實現，其晶片面積為1.19×1.06mm2。在輸入10Gb/s 27-1的擬似隨機位元序資料下，模擬的時脈峰對峰抖動為2.54ps,pp。在相同的輸入資料下，而模擬的資料峰對峰抖動分別為2.29ps,pp (CDR)與3.15ps,pp (DLL)。在工作電壓1.0V的情況下，功率消耗為90mW (CDR) + 30mW (DLL)。
並列摘要
In order to realize a clock and data recovery (CDR) circuit for high-speed wire-line communications, this thesis proposes a half-rate CDR circuit with automatic frequency acquisition at first design. The Half-rate CDR circuit generates the desired output phase with phase interpolators and completes the half-rate frequency error detection without using ring oscillator. The CDR circuit is fabricated in 90nm CMOS technology with an area of 0.96×0.84mm2. When the CDR circuit receives 10.3125Gb/s 27-1 PRBS input data, the measured clock’s peak-to-peak and rms jitter are 14.54ps,pp and 1.90ps,rms. In the same input data, the measured data’s peak-to-peak and rms jitter are 26.85ps,pp and 5.12ps,rms. The power dissipation is 244mW under a 1.2V and the jitter tolerance exceeds IEEE 802.3ba’ s jitter tolerance mask by 0.46UIpp. We already realize a single-channel CDR circuit, but there are four channels in the physical layer of the IEEE 802.3ba’s architecture. This thesis presents a multi-channel CDR architecture which combines a CDR circuit and three delay locked loop (DLL) circuits in order to save power, hardware cost and avoid interference between multiple oscillators. A CDR circuit provides I/Q clocks for DLL circuits to complete multi-channel CDR architecture. However the half-rate nonlinear CDR circuit’s output jitter is too large to provide reliable clock output for DLL circuits. This thesis proposes a hybrid phase error detection circuit, so that the linear CDR circuit can be used in high-speed operation. In considering the cost of hardware, we chose to implement 2×10Gb/s multi-channel CDR architecture. The multi-channel CDR circuit is fabricated in 90nm CMOS technology with an area of 1.19×1.06mm2. When the multi-channel CDR architecture receives 10Gb/s 27-1 PRBS data, the simulated clock’s peak-to-peak jitter is 2.54ps,pp. In the same input data, the simulated data’s peak-to-peak jitter are 2.29ps,pp (CDR) and 3.15ps,pp (DLL). The power dissipation is 90mW (CDR) + 30mW (DLL) under a 1.0V.