摘要
近年來摩爾定律依然持續，現今積體電路設計複雜度已超乎想像，而在積體電路設計流程中會遇到的一個瓶頸是在驗證階段必須要從原始電路提取RC網絡列表進行模擬，這會花費大量的時間及記憶體，因此將RC網絡縮減同時維持準確度是必須的，自從時間常數平衡消去法(TICER)在1999年發表後到現在依然是商用EDA軟體的主要的演算法。在以前，電路頻率要求並不高，然而現今的電路頻率已普遍來到千兆赫茲，對於縮減後的RC網絡在各方面的特性維持越來越重要。因此，在本論文中，我們在TICER的基礎上提出一個可以對電路中端口進行高精確度的縮減方法，我們將電路中的每個小區塊分別取出，再將各取出的區塊電路經TICER縮減的二階RC電路進行調整，調整的方式是以改變RC的分佈狀況來增加或減少高頻響應，因單位階躍中含有許多高頻成分，所以我們推論電路的高頻響應會影響到對單位階躍輸入的延遲，最後再將調整過同時維持艾莫爾延遲(Elmore Delay)的二階RC電路放回原電路。在真實存在的電路樣本的實驗結果顯示，比較調整前與調整後，我們的方法在大部分端口上有明顯的進步，甚至達到<1%延遲誤差。
並列摘要
As Moore's Law is still working in recent years, the complexity of integrated circuit design is very complicated today, and a bottleneck encountered in the integrated circuit design flow is that the RC netlist must be extracted from the original circuit for simulation during the verification phase, which is memory and time consuming. So it’s imperative to reduce the RC network while maintaining accuracy. Since TIme Constant Equilibration Reduction (TICER) was introduced in 1999, it’s still the mainstream algorithm of the current commercial EDA software. Circuit frequency requirements were not high in the past, but today's circuit frequencies have generally reached gigahertz. It is more and more essential to maintain the characteristics of the RC network in all aspects. Therefore, in this thesis, we propose a high-precision reduction method for the ports in the circuit based on TICER. We take out each part in the circuit separately by terminals and then reduce the circuit of each part through TICER. After reduction, all parts will be modified. The modified method is to change the distribution of RC to increase or decrease the high-frequency response. The unit step function contains many high-frequency components, so we infer that the high-frequency response of the circuit and delay of the unit step function are correlated. Finally, the second-order RC circuits that have been modified while maintaining the Elmore Delay are put back into the original circuit. The experimental results of the real circuit samples show that comparing before and after adjustment, our method has a significant improvement on most ports and even achieves <1% error rate of delay.