- 學位論文
一個0.052 mm^2 2.8至4.2 GHz子取樣環形振盪器的鎖相迴路採用雜訊抑制技術
A 0.052 mm^2 2.8-to-4.2 GHz Sub-Sampling Ring Oscillator PLL with Spur Reduction Technique
摘要
近年來由於通訊系統速度越來越快速且智慧型手機、平板電腦、穿戴式設備等便攜式產品的快速普及與朝向輕薄短小的情況下，造成市場對低成本、低功耗、小面積的積體電路需求日以劇增。現今產品大多使用先進製程來提高速度與減少面積，但也造成成本大大的增加。鎖相迴路也廣泛的應用在混和訊號模組化電路與通訊系統中，因此設計者如何在電路性能與成本考量做個取決是目前主要的課題。 由於傳統鎖相迴路的相位雜訊受到除頻器的除數影響，因此採用次取樣的方式，分成鎖頻率的迴路、鎖相位的迴路，來減少輸出相位雜訊。除此之外加入延遲鎖定迴路，降低輸出訊號的參考突波。在鎖相迴路中的壓控振盪器，主要分為電感電容振盪器與環形振盪器兩種，我們引用了電流式邏輯環形振盪器來實現小面積與較廣操作頻率。不僅如此電流式邏輯環形振盪器也較其他壓控振盪器穩定。 在本篇論文中使用台積電180奈米標準互補式金屬氧化半導體1P6M製程製造與量測，晶片主動區域面積為0.052〖mm〗^2，包含I/O PAD面積為0.6519〖mm〗^2。本晶片使用1.8伏特做為電源供應電壓。在除數為40下輸入頻率為92.5MHz輸出頻率為3.7GHz，參考突波為-53.80dBc。此鎖相迴路達到在1MHz偏移頻率下-109.95dBc/Hz之相位雜訊。RMS Jitter為1.1ps (1KHz-30MHz) 。此鎖相迴路的雙端輸出振幅達到300mV，總功率消耗為7.2mW。
並列摘要
Due to the sustained increase in communication systems, the portable products such as smart phones, tablets, wearable devices, etc., are rapidly becoming more popular, thinner and lighter. The demands for low-cost, low-power, small-area integrated circuits have been increased dramatically. In order to increase the speed and reduce the chip area, the designers use the advanced integrated circuit technologies to design chips. However, this causes a huge increase in cost. Phase-locked loop is also widely used in mixed signal modular circuits and communication systems. Therefore, the tradeoff between circuit performance and cost becomes one main issue for designers. The phase noise of the conventional phase-locked loop is affected by the divisor of the frequency divider. We use sub-sampling method to reduce output phase noise. The sub-sampling PLL consists of frequency-locked loop and phase-locked loop. We add delay-locked loop to reduce output reference spur. There are two main types of voltage-controlled oscillators in phase-locked loop, namely LC-type oscillators and ring-type oscillators. We use current-mode logic ring oscillator to achieve small area and wide operating frequency. This chip was fabricated in TSMC 0.18 μm CMOS 1P6M technology. The core area of the chip is 0.052 〖mm〗^2 and whole chip is 0.6519 〖mm〗^2. The input frequency is 92.5 MHz and output frequency is 3.7 GHz at supply voltage 1.8 V. The measured reference spur is -53.80 dBc. The measured phase noise performance of the PLL is -109.95 dBc/Hz at an offset frequency of 1 MHz and measured RMS jitter is 1.1 ps (1 kHz-30 MHz). The differential output swing is 300 mV and power consumption is 7.2 mW.