- 學位論文
雙圖案微影技術下考慮原生衝突之導線攪動
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology
摘要
對於小於22奈米的製程節點，雙圖案技術（double patterning technology）是目前用來增進可印刷性的熱門微影（lithography）方法。該技術係將一密集的佈局圖案分配到兩個獨立的光罩上，使各光罩上圖案的最小腳距（pitch）可以增加一倍，進而得到更好的印刷效果。在早先的研究中，為了改善分配的成功率，主要集中在縫合（stitch）插入方法的探討。然而，原生衝突（native conflict）的存在，將造成圖案分配的失敗，因為該衝突無法被任何一種縫合插入方法所解決，所以若設計中存在原生衝突，則勢必要訴諸於考慮製造性的重新設計，導致設計週期的延長。因此，開發一個於早期檢查圖案可分配性的分析工具是必要的。在本論文中，我們提出一個基於幾何結構的原生衝突預測方法以檢驗佈局的可分配性。此預測方法首先利用圖案投影的方式找出一組縫合插入的候選位置，並且保證可用這些候選位置建構出使衝突最少的組合。接著，利用此組候選位置，我們可探究原生衝突存在的充分條件。在原生衝突的預測後，我們提出一導線攪動（wire perturbation）演算法，其可盡可能地移除佈局中的原生衝突。該演算法係基於迭代式一維壓縮（compaction），且可很容易地嵌入於現有的壓縮系統中。實驗結果顯示我們提出的導線攪動演算法可以顯著地減少原生衝突的數目，並且在多數的測試電路上達到零衝突的效果。
並列摘要
The double patterning technology (DPT) is the most popular lithography solution for the sub-22$nm$ node to enhance pattern printability. In DPT, a dense layout pattern is decomposed into two separate masks so that its pitch can be doubled and thus lead to better printability. Previous works focus on stitch insertion to improve the decomposition success rate. However, there exist native conflicts (NC's) which cannot be resolved by any kind of stitch insertion. A design with native conflicts is not DPT-friendly and will eventually fail the decomposition, resulting in DFM redesign and longer design cycles. Therefore, it is desirable to develop an early stage analyzer for DPT decomposability checking. In this thesis, we propose a geometry-based method for NC prediction to examine the layout decomposability. The prediction method first exploits the set of stitch candidate positions by pattern projection. It guarantees that the optimal stitch combination with the fewest conflicts is within this set. Then, a sufficient condition for the NC existence is explored. After performing the NC prediction, a wire perturbation algorithm is presented to fix as many NC's in the layout as possible. The algorithm is based on iterative 1D-compaction and can easily be embedded into existing industrial compaction systems. Experimental results show that the proposed wire perturbation algorithm can significantly reduce the number of NC's and achieve NC-free for most test circuits.