- 學位論文
以米勒除頻器為基礎適用於超寬帶系統之時脈產生器
A Miller Divider Based Clock Generator for MBOA-UWB Application
摘要
超寬帶系統為美國軍方使用多年的技術，運用於地面穿透雷達、穿牆影像偵測等特種任務；應用在現今商業用途上，將可開發作為短距高速多媒體資訊的無線傳輸界面，形成無縫隙通訊的重要技術環節。為了統一此近距離高速無線通信的規格，多頻帶OFDM聯盟 (MultiBand OFDM Alliance; MBOA)向業界提議了一個稱為多頻正交頻率分工多工 (Multi-Band OFDM) 的傳輸標準。 在目前最普遍的多頻正交頻率分工多工用法類別模式一中，將三十億赫茲到五十億赫茲的頻段再細分成三個頻帶。系統規範要求最大的頻帶切換時間在9.5十億分之ㄧ秒內。傳統合成此三個載波頻率的方式為採用單側頻混頻器架構。但是單側頻混頻器會因為電路的不匹配而產生載波漏流或是非理想的側頻帶。 在這篇論文中，我們提出了一個以米勒除頻器為基本架構的時脈產生器。此時脈產生器可以產生應用於超寬帶系統的三個載波頻率，同時達到系統所要求的高速頻帶切換時間。此架構是在傳統米勒除頻器的回授路徑上加上一個混頻器，而輸出頻率則是由帶通濾波器控制。同時我們也提出了一簡單的分析方式，將電路轉換成頻域的等效模型，估計出頻帶切換所需的時間。為了節省晶片面積，在電路設計中，我們也採用了主動電感的技巧，關於使用的主動電感分析及功率消耗的最佳化也在此論文中提出。此時脈產生器已在0.18微米製程中實現，核心電路所消耗功率僅22毫瓦。
並列摘要
Although it began as a military application dating from the 1960s, UWB has been redefined as a high data rate, short-range technology that specifically addresses emerging applications in the consumer electronics, personal computing and mobile device markets. Under the auspices of the MultiBand OFDM Alliance (MBOA), personal computers and mobile devices have endorsed an approach called MultiBand Orthogonal Frequency Division Multiplexing (MB-OFDM) as the UWB solution. The MBOA UWB mode-1 system divides the 3.1-to-4.7-GHz spectrum into three sub-bands. The system requires band-switching time to be less than 9.5 ns. The traditional solution to synthesize the three carrier frequencies are employing single-sideband (SSB) mixing architecture. However, SSB mixing suffers from large carrier leakage and unwanted sideband due to the circuit mismatches. In this thesis, a Miller divider based clock generator is proposed to generate the three carrier frequencies of the MBOA-UWB mode-1 system while achieving less than 9.5-ns frequency settling time. The proposed approach adds a feedback mixer in the traditional Miller divider structure and the desired output frequency is determined by the band-pass filter. A simple method is also introduced to estimate the frequency-switching time by transforming the circuit into a frequency-domain equivalent model. For saving chip area, active inductors are used in the circuit design and an optimization technique is also presented to optimize the proposed active inductor with minimum power consumption. The proposed concepts are demonstrated in a 0.18-μm CMOS technology.