摘要
隨著晶片的面積以及時脈的頻率變快，高速時脈誤差消除電路與高速並且乾淨的時脈產生器的需求將變大，由於延遲鎖相迴路具有小面積、無抖動累積以及必然穩定的特性，所以在未來的應用上延遲鎖相迴路將變的越來越重要。 此論文提出了一個設計方法應用於延遲鎖相迴路為基礎的高速時脈產生器，藉由使用多週期鎖定的技巧，對於操作速度、多重相位的數目、充電泵以及相位比較器的工作速度上的限制將都被降低，所以延遲鎖相迴路將可操作在更高的速度，因此實現了一個40GHz鎖相迴路為基礎的高速時脈產生器。 接著，兩個寬範圍操作多相位延遲鎖相迴路的製作方法被提出，首先一個可以選擇鎖定週期數目的多週期延遲鎖定迴路被提出，藉由鎖定週期的選擇以及多週期的鎖定，將可提升迴路可以工作的範圍以及速度已達到更高速與寬範圍的操作，由於在高速上充電泵電流不匹配將導致嚴重的相位誤差，所以一個具有電流校正的充電泵被提出以降低相位誤差當延遲鎖相迴路高速運作時。此外我們提出了工作週期轉換成相位延遲的延遲單元，藉由工作週期轉換成相位延遲的方法，延遲單元將可工作在非常低的工作頻率以及寬範圍的操作，此外其具有小面積省電以及寬範圍操作的特點，延遲單元增益以及輸入週期的關係在此將被建立，因此使得在高速操作時抖動的特性將不會被降低。 最後，為了提升延遲鎖相迴路的速度，並聯的電壓控制延遲線的觀念被提出，因此在壓控制延遲線以及相位比較器與充電泵所需的速度將被降低，但是週期抖動將增加，為了降低週期抖動，我們提出了週期抖動校正的方法。
並列摘要
As the chip size and the clock frequency grow, the high-speed de-skew circuits and the high-speed clear clock sources are required. Due to the DLLs have the merits of the small area, no jitter accumulation and unconditional stable. So, the applications for the DLL will become more and more popular in the future clock design. This dissertation provides the design method of the high speed DLL-based clock generator. By using the multi-period-locked technique, the limitation of operating frequency, number of multi-phase, CP and PD will relaxed. The DLL can achieve a higher operation. Therefore, a 40GHz clock DLL-based clock generator is realized. Next, two methods are presented for the wide range multi-phase DLL. First, the multi-period-locked MDLL with a selectable locked period is presented. By using the selectable locked period in multi-period technique, the speed limitation and range at high frequency are relaxed, so the DLL can operate at higher frequency. Due to the current mismatch of the CP will result the serious static phase error when DLL locks at high frequency. The calibrated CP is also presented to reduce the static phase error. Second, the duty cycle to phase delay cell is presented. By transfers the duty cycle to phase, the delay cell can work at very low frequency and has the advance of small area, low power and wide range operation. The relation between the gain of a delay cell and input period will also be set up. Thus, the jitter performance at the high speed operation can be maintained. Finally, to enhance the operation speed of a DLL, the parallel VCDLs are adopted. The speed requirement for VCDLs and the PDs is relaxed, but cycle jitter may increase. To reduce the cycle jitter, the cycle jitter calibration method is presented.
參考文獻
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