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  • 學位論文

氧化層厚度對邊緣環繞超薄金屬閘極金氧半穿隧二極體雙態特性之影響

Effect of Oxide Thickness on The Two-State haracteristics in MIS(p) Tunnel Diode with Ultra-thin Metal Surrounded Gate

指導教授 : 胡振國

摘要


本篇論文中,我們製備了具有不同氧化層厚度的邊緣環繞超薄金屬閘極金氧半穿隧二極體。此種結構元件的瞬間雙態特性可以被放大。在論文的第二章中,具有不同氧化層厚度的邊緣環繞超薄金屬閘極金氧半穿隧二極體以及傳統金氧半穿隧二極體的電特性和瞬間雙態特性,證明了邊緣環繞超薄金屬閘極金氧半穿隧二極體在適當的氧化物厚度範圍內可以呈現較大的雙態電流差值。邊緣環繞超薄金屬閘極金氧半穿隧二極體的電特性對氧化層厚度非常敏感。此外,電流-電壓遲滯現象與瞬間雙態特性由於元件邊緣處的RC延遲使得兩者密切相關。在論文的第三章中,比較了最佳氧化層厚度 (29Å) 的邊緣環繞超薄金屬閘極金氧半穿隧二極體以及傳統金氧半穿隧二極體的瞬間暫態特性。瞬間鬆弛現象證明了RC延遲的存在。此外,元件的信號維持時間為 190 毫秒,這達到了動態隨機存取記憶體維持時間 64 毫秒應用標準的要求。在論文的第四章中,透過調變超薄金屬閘極區域面積和脈衝電壓的操作,在調變脈衝偏壓下可以放大瞬間暫態的響應。至於其他的關係則需要再更進一步的研究。

並列摘要


In this thesis, ultrathin metal surrounded gate Metal-Insulator-Semiconductor (UTMSG MIS) tunnel diodes with various oxide thicknesses were fabricated. The transient two-state characteristics of targeting devices can be magnified. In chapter 2, the electrical characteristics and transient two-state characteristics in the UTMSG MIS and the regular gate Metal-Insulator-Semiconductor (RG MIS) tunnel diodes with various oxide thickness were demonstrated that the UTMSG MIS devices can maintain larger two-state current window within appropriate oxide thicknesses range. The electrical properties of the UTMSG MIS devices are very sensitive to oxide thickness. Besides, the I-V hysteresis is closely related to the transient two-state characteristics because of RC delay at edge. In chapter 3, the optimal oxide thickness (29 Å) for transient characteristics in the UTMSG MIS devices was studied by comparing the RG MIS devices. Transient relaxation proves the existence of the RC delay. Also, the retention time of the UTMSG MIS device reaches a value of 190 ms, which fulfills the requirement of the DRAM applications. In chapter 4, by modulating ultrathin metal area and programming operation, transient responses have been enlarged during bias operation. Other relationship should be further investigated in more detail.

參考文獻


[1] R. Giterman, A. Fish, N. Geuli, E. Mentovich, A. Burg and A. Teman, “An 800-MHz Mixed-VT 4T IFGC Embedded DRAM in 28-nm CMOS Bulk Process for Approximate Storage Applications,” IEEE Journal of Solid-State Circuits, vol. 53, no. 7, pp. 2136-2148, May 2018.
[2] R. Giterman, A. Fish, A. Burg and A. Teman, “A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 4, pp. 1245-1256, Apr. 2018.
[3] Y. D. Tan and J. G. Hwu, “2-State Current Characteristics of MOSCAP with Ultrathin Oxide and Metal Gate,” ECS Solid State Lett., vol. 4, no. 12, pp. N23-N25, Nov. 2015.
[4] K. H. Tseng, C. S. Liao and J. G. Hwu, "Enhancement of Transient Two-States Characteristics in Metal-Insulator-Semiconductor Structure by Thinning Metal Thickness," IEEE Transactions on Nanotechnology, vol. 16, no. 6, pp. 1011-1015, Nov. 2017.
[5] K. H. Tseng, “Two-State Current Behavior in MIS Tunnel Diode with Ultra-thin Surrounding Gate Metal Electrode,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ. Taipei, Taiwan, R.O.C., Jul. 2016.

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