- 學位論文
應用於高頻之寬頻帶放大器技術與實作
The Techniques and Implementations of the Broad-band Amplifiers for High-frequency Applications
摘要
隨著市場對通訊的需求越來越高，高傳輸速率的通訊系統因而受到越來越多的關注，而寬頻架構擁有同時進行複數閘道傳輸的特性更不啻為一增加傳輸速率的解決方案；近年來金氧半場效電晶體製程的高度發展，越來越多的高速系統使用其製程來實現及整合，而放大器更是每個系統中不可或缺的關鍵元件。有鑒於以上的技術考量及發展趨勢，我以深次微米的金氧半場效電晶體製程來實現高速寬頻放大器，作為我畢業論文的研究主題，兼具實用性和挑戰性。 在簡述完各種寬頻技術後，在晶片實作部分，首先提出了一顆符合OC-768規格的差動分散式放大器，運用了寬頻堆疊式的增益級以及非均衡傳輸線的結構，大幅度的改善了頻寬和增益平坦度；據筆者的文獻探討，這顆電路是目前用金氧半場效電晶體0.18微米製程所製作的寬頻放大器中，唯一能差動放大且達到40Gb/s傳輸速率的作品。 接著闡述另一顆適用於光通訊前端電路並具有頻寬調變機制的轉阻放大器，而這樣的設計目標主要是為了能因應環境雜訊及製程偏移的影響，藉著頻寬的改變而達到相對較好的誤碼率；其主要的結構包含寬頻的輸入端電流電壓轉換器，寬頻的放大器及頻寬調節迴路，來實際達成此構想。 為了完成一操作在10Gb/s的光通訊前端電路，我使用了改良式的Cherry-Hooper放大器架構去實現一顆限制放大器，而透過跨級回授的方式，整體的頻寬更能有效的改善以符合規格需求，與已發表的文獻相比，此電路能在達到相同規格的條件下，大幅度的減少所需消耗的功率，對系統整合及及實用性而言都有莫大的貢獻。
並列摘要
Owing to the extensive requirement of data capacity, the communication system with high data rate has aroused much more attention. Broadband architecture is one of the important techniques for high speed application since it enables multi-channel transmissions simultaneously, and the wideband amplifier is usually the critical component among all of the building blocks. Besides, following the highly-developed Si-based process, various high speed systems are realized and integrated by CMOS technology. Now that the above descriptions are the significant trends in recent years, the researches and developments of high-frequency wideband amplifier in submicron CMOS process are quite a practical and challenged topic of the thesis. In order to realize the broadband techniques, a differential distributed amplifier (DA) is developed for OC-768 applications. The non-uniform design strategy is utilized and the inductive peaking cascode topologies are applied to improve the performance. According to the demonstrated references, the proposed differential DA is the only work able to operate in 40-Gb/s data rate in CMOS 0.18-μm process. Afterward, a transimpedance amplifier (TIA) with tunable 3-dB bandwidth is presented for optical communications. Within a broadband input loading and a wideband gain stage, a feedback loop is incorporated as the bandwidth-tuning mechanism. By tuning the bandwidth of the TIA, an optimum bit-error-rate (BER) can be achieved in the receiver frontend for high-speed data transmission. To complete a receiver front-end, a 10-Gb/s limiting amplifier (LA) is involved with modified Cherry-Hooper amplifier structure. By the inter-stage feedback mechanism, the bandwidth is further widened for the standard requirement. In comparison with the published works, the power consumption is enormously saved within the proposed LA architecture.