- 學位論文
雙延遲路徑的環型振盪器與多相位補償之除小數頻率合成器
The Design and Analysis of Dual-Delay Path Ring Oscillators and a Multiphase Compensation Method for Fractional-N Frequency Synthesizers
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摘要
環型振盪器(ring oscillators)和頻率合成器(frequency Synthesis)廣泛的被應用於許多通訊系統，比如時脈產生器(clock generator)或是迴路內之調變器(in-loop modulator)。此篇論文分別介紹了雙延遲路徑的環型振盪器(dual-delay path ring oscillators)以及多相位補償之除小數頻率合成器(multiphase compensation method for fractional-N frequency synthesizers)。 環型振盪器廣泛的被應用於時脈產生器或是頻率合成器當中。為了增加振盪頻率，雙延遲路徑的環型振盪器經常被使用以提升其最高振盪頻率。在四級雙延遲路徑的差動環型振盪器中(differential 4-stage dual-delay path ring oscillator)，被發現有兩種振盪模式，它們分別為：差動式振盪模式(differential mode oscillation)以及共模式振盪模式(common mode oscillation)。當振盪器運做於差動式振盪模式下時，延遲元件(delay cell)輸出差動波形(differential output waveforms)。而當振盪器運做於共模式振盪模式時，延遲元件則輸出同相位波形(in-phased output waveforms)。除此之外，兩種振盪模式之振盪頻率也不同。這樣的情形會造成時脈產生器或是頻率合成器無法正常運作。為了對雙延遲路徑的環型振盪器有更深入的了解，我們用數學分析推導以及實作量測來解析四級雙延遲路徑的差動環型振盪器的兩種振盪模式。此四級雙延遲路徑的差動環型振盪器佔用了58 × 41 um2 之晶片面積，實現在0.18 um CMOS 製程中。在差動式振盪模式下，所量測的輸出頻率範圍為 1.77 GHz ~ 1.92 GHz，並且消耗13 mW 及使用1.8 V 之供給電壓。而在共模式振盪模式下，所量測的輸出頻率範圍為 1.01 GHz ~ 1.055 GHz，並且消耗10 mW 及使用1.8 V 之供給電壓。 具有高效能之頻率合成器在許多通訊系統中，比如WCDM之傳輸接收器(transceivers)或迴路內調變器，扮演著重要的角色。在本篇論文當中提出了一多相位補償之除小數頻率合成器。為了改善電路元件中因不匹配而產生之非理想效應，提出了一延遲線路(delay line)和一包含了動態器件匹配技術(dynamic element matching technique)和再量化之三角積分調變器(re-quantized S-D odulator)的數位控制電路(digital control circuit)。此多相位補償之除小數頻率合成器操作在2.11 GHz到2.17 GHz之時脈，佔用了0.92 × 1.15 mm2 之晶片面積，實現在0.18 um CMOS 製程中。在所提出之架構中，於距離2.14-GHz輸出10-MHz頻帶處的量化誤差消減了10 dB。所須鎖定時間少於25 usec。
並列摘要
Ring oscillators and frequency synthesis are widely employed in communication systems, such as clock generators or in-loop modulators. In this thesis, a dual-delay path ring oscillator and a multiphase compensation method for fractional-N frequency synthesizer are covered. Ring oscillators are widely used in clock generators and frequency synthesis. To increase the oscillation frequencies, dual-delay path ring oscillators are often implemented to explore the maximum frequency levels. Two oscillation modes have been found in differential four-stage dual-delay path ring oscillators, one named differential mode oscillation and the other named common mode oscillation. In differential mode oscillation, a single delay cell contains differential output waveforms, but in common mode, the output waveforms are in-phased. In addition, the oscillation frequencies of the two oscillation modes are not the same either. These problems might spoil the function of the clock generators and frequency synthesis. For more insight of dual-path ring oscillators, mathematical analysis and demonstrations including the two oscillation mode in a differential four-stage dual-delay path ring oscillator is presented. A differential four-stage dual-delay path ring oscillator is fabricated in a 0.18-um CMOS technology with an active area of 58×41 um2. The measured tuning range is from 1.77 GHz to 1.92 GHz in differential mode oscillation which consumes 13 mW from a 1.8-V power supply, and from 1.01 GHz to 1.055 GHz in common mode oscillation that consumes 10 mW from a 1.8-V power supply. High performance frequency synthesis is required in communication systems such as WCDMA transceivers or in-loop modulation systems. In this thesis, a S-D fractional-N frequency synthesizer with a multiphase compensation method is proposed. To resolve the problem brought by nonidea effect such as delay unit mismatch and gain error, a proposed delay line structure and a digital control circuit including dynamic element matching techniques and a re-quantized S-D modulator is presented. A frequency synthesizer operating from 2.11 GHz to 2.17 GHz, is fabricated in a 0.18-um CMOS technology with an area of 0.92×1.15 mm2. Power consumption is 27.2 mW from 1.8-V power supply. The proposed architecture suppresses the quantization noise of 2.4-GHz output at 10-MHz frequency offset by 10 dB. The settling time is less than 25 usec.
參考文獻
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