- 學位論文
整合扇出型晶圓尺寸封裝設計之繞線系統
A Redistribution Layer Routing System for Integrated Fan-Out Wafer-Level Chip-Scale Packages
摘要
整合扇出型晶圓尺寸封裝 (integrated fan-out wafer-level chip-scale package) 是一個新興的封裝技術，此封裝技術通常會藉由多層重分佈層 (redistribution layer) 來進行多個晶片間的訊號傳輸。目前尚未有發表的論文是針對整合扇出型晶圓尺寸封裝的重分佈層繞線做探討，大部分相關的發表論文著重於考慮覆晶 (flip-chip) 封裝上的重分佈層繞線問題，傳統的覆晶封裝中通常只有單一個晶片，而覆晶封裝上的重分佈層繞線問題可以分為三類，分別是自由配對繞線問題、非自由配對繞線問題與混合型配對繞線問題。由於整合扇出型晶圓尺寸封裝整合了多個晶片，相關的繞線器無法有效地處理此技術的重分佈層繞線問題。為了彌補相關論文缺乏對於多個晶片及多層重分佈層的考慮，我們提出了一個新的整合扇出型晶圓尺寸封裝中的重分佈層繞線問題，此問題考慮到了訊號的完整性、訊號線的分層、重分佈層數量的最小化與總線長的最小化，同時此篇論文提出了第一個針對此問題的演算法。我們提出了一個同心圓模型 (concentric-circle model) 來模擬一個晶片跟其他所有晶片之間的連線，基於此模型，我們將晶片之間的連線分配到適當的重分佈層來避免訊號線過長。除此之外，此模型將晶片間非自由配對連線的幾合資訊整合到了一個網路流模型，此網路流模型可以產生在扇出區域中的繞線雛型。實驗結果顯示我們的演算法的高品質與高效率。
並列摘要
The integrated fan-out (InFO) wafer-level chip-scale package (WLCSP) is an emerging packaging technology, which typically consists of multiple redistribution layers (RDLs) for signal redistributions among multiple chips. There is still no published work specifically on the RDL routing for the InFO WLCSP. Published RDL routing works consider different types of RDL routing for flip-chip packages, namely free-assignment, pre-assignment, and unified-assignment routing, for a single chip. With the integration of multiple chips under the InFO WLCSP, however, previous works cannot achieve high efficiency and effectiveness with simple extensions. To remedy the deficiencies of poor interactions between chips and multiple RDLs, we formulate a new RDL routing problem for the InFO WLCSP and present the first work in the literature to handle the unified-assignment, multi-layer multi-chip RDL routing problem (without RDL vias), considering signal integrity, layer assignment, layer number minimization, and total wirelength minimization. We propose a concentric-circle model which models all the connections among one chip and all other chips. Based on this model, we assign the connections between chips and appropriate layers to avoid long detours. In addition, this model transforms the geometrical information of the pre-assignment connections among chips into a network-flow model to generate a routing prototype in a fan-out region not covered by any chip efficiently and effectively. Experimental results demonstrate the high quality and efficiency of our algorithm.