- 學位論文
PCIe Clock訊號完整度分析與改善
Analysis and Improvement of PCIe Clock Signal Integrity
摘要
本論文深入分析並改善了PCIe Clock訊號的完整性，重點探討了專案中遇到的RMS Phase Jitter問題。量測發現Clock訊號的RMS Phase Jitter超出PCIe 4.0規範，為此進行了一系列除錯實驗，包括阻抗量測、更換旁路電容、開關展頻功能、更換PCIe連接線材及移除CPU。 研究發現問題源自Return Path。並採取割線實驗將靠近Clock訊號的GND Shape和Power Via的面積減少，使其增加它們與Clock訊號的間距，雖然數值下降，但仍未達標。最終，在新版本主板的設計中將Clock訊號走線改至內層，與GND Shape完全隔絕，並增加與Power Via的間距，成功改善Clock訊號完整性，符合PCIe 4.0規範。 本論文提供了一套針對PCIe Clock訊號RMS Phase Jitter問題的系統化解決流程，強調設計階段考慮return path的重要性，支持訊號完整性理論，為PCIe設計提供創新思路，對工程師和設計者具有參考價值。
並列摘要
This paper conducts an in-depth analysis and improvement of the signal in-tegrity of PCIe clock signals, focusing on the RMS phase jitter issue en-countered in the project. Measurements revealed that the RMS phase jitter of the clock signal exceeded the PCIe 4.0 specification, prompting a series of debugging experiments including impedance measurements, replacing by-pass capacitors, switching the spread spectrum feature on and off, replacing PCIe cables, and removing the CPU. The study found that the problem originated from the return path. A cut-ting experiment was conducted to reduce the area of the GND shape and power via near the clock signal, increasing their distance from the clock sig-nal. Although this reduced the RMS phase jitter, it still did not meet the standard. Finally, in the design of a new version of the motherboard, the clock signal routing was moved to an internal layer, fully isolating it from the GND shape and increasing the distance from the power via, successfully im-proving the clock signal integrity to comply with the PCIe 4.0 specification. This research provides a systematic solution process for the RMS phase jitter issue of PCIe clock signals, emphasizing the importance of considering the return path during the design phase. It supports signal integrity theory and offers innovative ideas for PCIe design, serving as a valuable reference for engineers and designers.