- 學位論文
一個具真亂數隨機產生器校正之低失真10位元100MHZ數位類比轉換器
A Low Distortion 10-bit 100MHz Current Steering DAC with True-Random-Number -Generator Randomizer
摘要
電流導向式數位類比轉換器在寬頻帶的應用上因為具有很高的無突波動態範圍(Spurious free dynamic range, SFDR)，在動態元件匹配方法裡，資料權重平均法(DWA)被廣泛應用在超取樣技術中。為提高效能，奈奎斯特頻率技術(Nyquist frequency)的電流導向式數位類比轉換器會使用隨機的方法，再配合適當的佈局，來降低製程上所引起的電晶體不匹配效應，也可以降低整體數位類比轉換器的面積。 本論文提出一個10位元100MHz電流式數位類比轉換器的設計與實現，此電流式數位類比轉換器的輸出不需要額外的緩衝器，可以達成低功耗、高速及高解析度的規格，數位類比轉換器在動態及靜態的表現中會受到製程上不匹配的影響。因此，本論文採用比較器的真亂數生成器(True Random Number Generator)來改善其在製程上的影響，讓元件不匹配所造成的諧波(Harmonics)可以被分散並降低，藉以提升無突波動態範圍。而論文中使用混合式數位類比轉換器，因混合了二進位加權碼與溫度計編碼兩種架構的設計，目前較好的架構是結合這兩種架構的優點，將其缺點降低的混合式架構，能藉以提升積分非線性誤差、微分非線性誤差、突波。 沒加入真亂數生成器前，電流源可能會因為不匹配的原因，也可能是製程變異所造成的現象。為了提升更好的無突波動態範圍及其他參數，將原本的隨機電路(Randomizer)，用比較器的方式取代。輸入訊號先經過轉換，變成溫度計解碼器，在與(B6~B4)所轉出的溫度計編碼，經過真亂數生成器打亂其順序後，在進下一層電路做解碼。而比較器的作用是，在CLK 0與1轉換瞬間，開始比較，利用兩邊電晶體的電壓以及速度轉換差異，進行比較。當VIN+比VIN-大時，輸出1，相反，輸出0。而SR Latch 的作用是讓比較器的輸出不會因為CLK = 0 時的重置不斷改變。利用此方法，讓電流跟不匹配的現象得以改善。
並列摘要
The current-steering digital-to-analog converter has a very high Spurious free dynamic range in wide-band applications. In the dynamic component matching method, the data weight averaging method is widely used in. In oversampling technique. In order to improve performance, the current-steering digital-to-analog converter of Nyquist frequency technology will use a random method, combined with a proper layout, to reduce the transistor mismatch effect caused by the process, and can also reduce. The area of the overall digital-to-analog converter. This paper proposes the design and implementation of a 10-bit 100MHz current-mode digital-to-analog converter. The output of this current-mode digital-to-analog converter does not require additional buffers, and can achieve low power consumption, high-speed and high-resolution specifications. Analog converters suffer from process mismatches in both dynamic and static performance. Therefore, this paper uses the True Random Number Generator of the comparator to improve its influence on the process, so that the harmonics caused by component mismatch can be dispersed and reduced, so as to improve the glitch-free Dynamic Range. In this thesis, a hybrid digital-to-analog converter is used. Due to the design of the two architectures of binary weighted code and thermometer code, the current better architecture is a hybrid architecture that combines the advantages of these two architectures and reduces their shortcomings. It can be used to improve integral nonlinear error, differential nonlinear error, and surge. Before the true random number generator is added, the current source may be caused by mismatch or process variation. In order to improve better glitch-free dynamic range and other parameters, the original random circuit is replaced by a comparator. The input signal is first converted into a thermometer decoder, and the thermometer encoded by (B6~B4) is transferred out. After the real random number generator scrambles its sequence, it enters the next layer of circuit for decoding. The function of the comparator is to start the comparison at the moment of CLK 0 and 1 conversion, and use the voltage and speed conversion difference of the transistors on both sides to make the comparison. When VIN+ is greater than VIN-, output 1, otherwise, output 0. The function of SR Latch is to prevent the output of the comparator from continuously changing due to the reset when CLK = 0. Using this method, the phenomenon of current mismatch can be improved.