- 學位論文
低密度奇偶檢查碼之新型對數域演算法及解碼晶片設計
Chip Design for LDPC decoder employing New Log Domain Algorithm
摘要
本論文提出一種以快速解碼為訴求的LDPC解碼流程之超大型積體電路架構設計。在不影響解碼效能下提出一新型對數域解碼演算法流程，該一新型對數域解碼演算法流程可以免去傳統演算法中必須對記憶體上作儲存及讀取 值的動作，進而可以簡化流程程序以達到增加訊息吞吐量。 在驗證上我們以Xilinx Vertix-4 的FPGA系統來進行，硬體方面驗證在以cell-based流程完成晶片設計。實驗結果顯示，該一LDPC解碼流程可以有效的省下相較於傳統流程中30%的記憶體存取次數，進而可以有效節省整體14.5~18%的處理時間。最後我們也實際以TSMC .18μm 1P6M製程，完成一顆新型LDPC解碼流程晶片設計，整個電路含I/O PAD 的面積為 1.94x1.94mm2。
並列摘要
In this thesis ,we propose a new VLSI architecture for high speed Low Density Parity Check Code decode. A new log domain algorithm is developed for LDPC decoding without losing error correction performance. In comparison with traditional LDPC, this algorithm can decode the LDPC without saving and reading the value. Thus, we can simplify the decoding flow and increase the decoding throughput. For hardware implementation, we use Xilinx Vertix-4 FPGA to verify this new LDPC decoder firstly. Then we also design this chip by standard cell-based flow. Experiments show that this decoder can save 30% memory read and write operations in comparison with traditional decoder. Meanwhile, it can reduce 14.5~18% processing time. Finally, we have designed this new LDPC decoder by TSMC .18μm 1P6M process. And chip size including I/O PAD is 1.94x1.94mm2.