動態可重新組態數位IIR濾波器之架構設計

Design of the Architecture for Real Time Reconfigurable Digital IIR Filter

楊智凱(Chin Kai Yang)

指導教授 ： 王仲淳

元智大學/工程學院/電機工程學系/碩士(2003年)

摘要

本論文提出之動態可重新組態數位IIR濾波器之架構，在於利用FPGA( Field Programmable Gate Arrays ) 中的 SRAM( Static Random Access Memory )技術，實現Reconfigurable的功能，建構出一套處理大量資訊的Co-processor 系統。FPGA重新組態的技術可依照計算機制需求，動態的改變硬體架構提供最適合的服務；另外也可藉由硬體快速處理的能力，來提昇效能。
本論文對於系統的Co-processor是選擇數位IIR( Infinite Impulse Response )濾波器，之所以選擇數位IIR濾波器，最主要的原因是在於IIR濾波器硬體需求較低，適合於處理較高頻域的訊號。

關鍵字

重新組態

並列摘要

The Architecture for Real time Reconfigurable Digital IIR Filter is proposed in thesis. It used SRAM (Static Random Access Memory) technology of FPGA (Field Programmable Gate Arrays) to achieve a Reconfigurable function and to build up a Co-processor system to deal with large amount of information. Reconfigurable FPGA technology provided the capability to dynamically alter a computer’s hardware resource to optimally service the immediate computational needs. In addition, the Co-processor will achieve higher performance, due to hardware’s faster capability .
As to Co-processor of system, digital IIR (Infinite Impulse Response) filter was chosen. The main reasons for digital IIR filter being used because it needs lesser hardware and it deals with high in frequency signals.

並列關鍵字

FPGA ； VHDL ； IIR ； Co-processor

參考文獻

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