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  • 學位論文

1.8V 二階低通三角積分調變器

A 1.8V 2nd-Order Lowpass Sigma-Delta Modulator

指導教授 : 吳紹懋
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摘要


本論文設計一個低電壓的2階低通三角積分調變器(Lowpass Sigma-delta Modulator), 可應用於聲頻應用上,此調變電路接上Decimator Filter即可組成完整的類比數位轉換器。為了可攜帶性的考量,而電池的選取對於可攜帶性產品是很重要的, 本調變器僅使用單端電源1.8V,可有效降低電池重量,使用於有輕便性要求的產品上,且本調變器總耗電量僅約1.2mW,能有效的增加電池使用壽命。本調變器使用全差動交換式電容電路(Switched-capacitor)的電路來實現,信號頻率為4KHz,此頻率為一般的人類聲音頻率。在超取樣率為128時,所得到SNDR值為59dB,而解析度為11-bit,功率消耗小於1.2mW,佈局面積為1078um×1356.5um,而使用的製程為AMPI 0.6um1P2M的數位CMOS製程。

並列摘要


This paper presents a low-voltage 2nd-order lowpass sigma-delta modulator, which can be used for voice application. We can connect a decimator filter to be a complete A/D converter. The choice of battery is an important issue for portability products. The modulator only uses the single power supply (1.8V), which can decrease the weight. The power dissipation of the modulator is about 1.2mW, it can increase the life of battery. The modulator is implemented with switched-capacitor technique; the signal frequency is 4KHz, which is the voice band. The OSR is 128, the peak SNDR is 59dB, and the resolution is about 11-bit. The power dissipation is lesser than 1.2mW, and area is 1078um×1356.5um. The modulator is implemented in the AMPI 0.6um 1P2M standard CMOS digital process.

並列關鍵字

ADC

參考文獻


[1] V. Peluso, et al, “ A 900-mV Low Power ΣΔ Converter with 77-dB Dynamic Range,” IEEE JSSC, Vol.33 p1887-1897,1998.
[2] P. C. Maulik, et al, “ An Analog/Digital Interface for cellular Telephony,” IEEE JSSCC, vol.30, p201-209,1995.
[3] S. Rabii and B. A. Wooley. “ A 1.8V, 5.4mW, Digital-audio sigma-delta modulator in 0.8um CMOS,” IEEE JSSC, vol. 32 , p783-796,1997.
[4] James C. Candy and Gabor, Overampling Delta-Sigma Data Converters, IEEE Press,1991, ISBN 0-87942-285-8
[5] David A. Johns and Ken Martin, Analog Integrated Circuit Design, John Wiely & Sons, 1996,ISBN 0-471-14448-7

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