並列摘要
RISC的機器已被廣泛的使用後，若要使RISC的機器能夠更快速的處理指令 ，實在有賴於一個良好的編譯器來產生高效率的機器碼。而對於新一代的 RISC電腦—超純量系統(Superscalar machines)而言， 編譯器的設計更 為重要。 在近幾年的研究報告中顯示， 在一個基本區塊 ( basic block ） 中的指令階段的平行度 （ instruction - level parallelism ）是很小的，跨越過多個基本區塊來找到更大的指令平行度 ， 以充份發揮超純量系統上的多功能單元 ( multiple functional unit)，為一重要研究主題。我們的研究，主要在探討超純量系統上指令 階層的排程技術，以利於在同一週期發出多個指令( multiple instruction issuing)，並增加指令平行度。們發展了一套簡單而有效 的基本區塊間的指令排程程序，套程序能有效的利用多個週期的指令(如 load, store)， 填充剩餘的時間槽，因為這些指令，通常屬於管家類( house Keeping)指令，容易移動於基本區塊間，同時這套方法能夠處理 IF-THEN的結構，我們實作結果，證明這套程序可行且有效。 RISC machines have been getting tremendous popular. One of the major goals of the RISC approach is to chieve high performance. The success of RISCs heavily depends on the effectiveness of the compiler. The second generation RISC machines, so called superscalar machines, use multiple functional units to achieve parallel execution of multiple instructions in one cycle. The key design issue for these machines is to arrange multiple instructions executed in parallel so as to effectively utilize the multiple units. The research investigates instruction level scheduling techniques in order to enhance instruction parallelism. In the research we have developed a simple and effective inter-block code motion procedure. Our procedure can effectively rearranges multi-cycle instructions (such as load and store ), to fill free time slots in the schedule. Since these instructions are usually used in house keeping style and thus can be moved among basic blocks. Also, the procedure handles IF-THEN structures. Our implementation concludes the feasibility study and effectiveness evaluation of our approach. Future study is needed to incorporated desirable architecture features with the instruction scheduling.