- 學位論文
16位元多級順向MASH超取樣Sigma-Delta類比數位調變器之晶片設計與實現
A Chip Design and Implementation of 16-bit MASH Oversampling Sigma-Delta Analog-to-Digital Modulator
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摘要
本論文研究設計一個高解析度2階Cascaded Sigma-Delta超取樣(Oversampling)類比數位調變器晶片。 此調變器的設計是以差動交換電容電路（Fully Differential Switched Capacitor）的技術來達成，並利用超取樣率（Oversampling Ratio, OSR）、雜訊移頻（Noise Shaping）、多級順向（Multi-stage Noise Shaping, MASH）等等類比調變器設計方法，以提升整體的效能。其解析度可達16-bit之高，而信號範圍為基頻48KKHz 範圍。此一規格的調變器將可應用於AC97 (Intel Audio Codec 97) 介面中。其系統取樣頻率為12.28MHz，超取樣率為128倍，訊號雜訊比為96dB，使用±2.5V雙電源，消耗功率為19.6955mW，佈局面積為647.1μm×358.7μm，晶片面積為1800μm×1800μm，使用的製程技術為聯華積體電路製造公司(UMC) 0.5μm 2P2M製程。
並列摘要
In this thesis, we propose a high-resolution 2nd-order cascaded Sigma-Delta oversampling Analog-to-Digital modulator chip. The modulator is implemented with fully differential switched capacitor circuits, over-sampling ratio, noise shaping, and multi-stage noise shaping. The modulator achieves a resolution of 16-bit and the signal bandwidth is 48KHz. The specification is fit for Intel Audio Codec 97 interface. The system is driven by 12.28MHz, and the OSR is 128, the SNR is 96.6dB the power supply is ±2.5V, the power consumption is 19.6955mW, the modulator layout area is 647.1μm×358.7μm, and the chip area is 1800μm×1800μm. The fabrication technology is UMC 0.5μm 2P2M technology.
參考文獻
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