摘要
隨著半導體的製程進步，繞線問題變得比以前更複雜。如果在晶片中有一條不能完成繞線的線路時，繞線器將會花很多時間在重新繞線的工作上。為了能夠有效的達到100% 繞線結果，繞線分析應該在元件 (cell) 放置後和繞線之前提供有關繞線資源和繞線需求的相關資訊。在這篇論文中，我們首先分析由一般商業工具已經繞好的晶片進行觀察以了解繞線行為。接著，一個放置後的繞線分析器根據已經繞好線路的繞線行為進行發展。此繞線分析器包含兩個主要的部分，一個是由繞線資源和繞線需求的計算器計算晶片中可用的繞線資源和繞線需求，並且建立擁擠圖來顯示擁擠的地區。另一個是由繞線資源調整器適當地增加繞線資源以移除擁擠地區或減少繞線資源以減少晶片面積。最後，由我們演算法所產生的擁擠圖也將會和實際繞好線路的晶片做比較來看我們演算法的效能。實驗結果顯示我們的繞線分析可以正確地預測大部分擁擠的區域。繞線資源調整器可以預測所需要的通道 (channel) 容量和實際需要的通道容量誤差大約在1.5條軌道 ( track)。
關鍵字
繞線分析並列摘要
With the advancement of semiconductor process, the routing problem is becoming more complex than ever before. If there is an unroutable net on a chip, a router will spend a lot of time on rerouting. In order to effectively achieve 100% routing, routability analysis should be performed for a design after placement and before routing to obtain the information about routing resources and routing demands. In the thesis, we first analyze the wires routed by a commercial router to understand the routing behavior. Then, a post placement routability analyzer based on the wiring distribution of routed nets will be developed. This analyzer consists of two major parts. A Routing Resource and Routing Demand Quantifier computes the routing demands for a given design. It builds a congestion map for showing congestion regions. A Routing Resource Tuner properly increases or decreases tracks in a region to either remove congestion or minimize chip area. The congestion map generated by our approach will be compared to the actual routing of a chip to see the effectiveness of our approach. The experimental results show that our routability analysis can actually predict most of the congestion regions. The Routing Resource Tuner can predict the required channel capacity within about 1.5 tracks difference from the exact number tracks needed for a complete routing.
並列關鍵字
routability參考文獻
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