- 學位論文
利用複製LUT之效能導向FPGA叢集演算法之研究
LUT Duplication Performance-driven FPGA Clustering
摘要
在傳統的FPGA設計流程中，clustering對於FPGA晶片的效能和面積這兩個部分影響極大。因為FPGA設計流程中，technology mapping和clustering這兩個程序是彼此分開考量， clustering需要technology mapping做完後的電路，但是其電路會影響到clustering後的結果。針對這個問題，我們提出利用複製LUT的方式來調整原本的電路，進而有利於clustering的演算法，進而可以降低delay。在實驗方面，則和DAOmap + T-VPack這兩個technology mapping和clustering的演算法相做比較，最後由實驗數據比較後，我們的演算法在效能方面比DAOmap + T-VPack增加了14.6%，而面積只多了3%。
關鍵字
叢集並列摘要
Island-style FPGA is one of a well-known pre-fabricated design styles with very high design flexibility. In a conventional FPGA design flow, circuits are mapped and clustered into configurable logic blocks (CLB) before being placed and routed. Hence, technology mapping and clustering result in great performance and area impacts in synthesis level. Since the delay models used for both two steps are different, optimizing a design in the two separated steps fails to obtain good final circuit. In this thesis, we propose a two-step method to optimize the clustering procedure. We duplicate the lookup tables (LUTs) in pre-clustering step to remove potential external interconnect between CLBs. Furthermore, we duplicate a predecessor LUT of a flip-flop once when the LUT has multiple fanouts to reduce the circuit levels with no area overheads. The experimental results demonstrate that our proposed method is capable of improving the circuit performance by 14.6% with only 3% area overheads as compared with the conventional FPGA design flow.