在半導體廠中,影響良率的因子除了製程配方的設定,亦包含了週期時間。當晶圓經過特定的製程步驟之週期時間越長,越容易收到粉塵的汙染與氧化,導致晶圓鋪設的電路受損,進而影響晶圓生產的良率。除此以外,某些製程步驟中的異常事件會同時降低晶圓生產之良率與增加其生產週期時間。因此如何透過週期時間尋找影響晶圓生產良率的關鍵之製程步驟成為良率分析之重要課題。 然而以生產週期時間進行良率分析存在了四個挑戰。第一個挑戰為良率分析基於週期時間效率問題。現今半導體廠有數百道製程步驟,若逐一將所有的製程步驟間週期時間與良率進行關聯性分析,將需要大量的演算時間。第二個挑戰為週期時間與良率之離群值效應。若分析過程中離群值沒有受到考量,將不利於良率分析的結果。第三個挑戰為共變量的效應。事實上週期時間並非唯一影響良率的因子,良率分析過程中忽略了其它因子對良率的影響會誤導良率分析的結果。第四個挑戰為週期時間與良率的非線性相關效應。若良率分析過程並未考量此效應,將不利於篩選的因子對於良率變量之解釋。 針對上述四項挑戰,本論文提出了一套基於週期時間之良率分析架構。此架構包含了關鍵週期時間分析、機台良率分析以及整合式良率建模等三個模組。第一個模組,關鍵週期時間分析包含了篩選與辨視兩步驟,分別解決前兩項挑戰。在篩選的步驟中,使用了皮爾森相關係數之近似值,快速標示出與良率高度相關的製程步驟間週期時間。在辨視的步驟中,則使用了斯皮爾曼等級相關係數,穩健的找出與良率有顯著相關的製程步驟間週期時間。第二個模組,機台良率分析使用變異數分析找出影響良率關鍵的機台。第三個模組,整合式良率建模協同前兩個模組,並包含了逐段線性建模以及逐步迴歸等兩個方法以解決第三項與第四項挑戰。逐段線性建模以兩組線性模型逼近週期時間與良率之非線性相關之效應,而逐步迴歸則針對影響良率關鍵的週期時間因子與機台因子進行變數篩選,對於不同性質的因子與良率進行分析。 模擬結果指出,相較於直接使用皮爾森相關係數對週期時間進行良率分析,關鍵週期時間分析不但可以得到相似的辨視率,且擁有較佳的分析效率。除此以外,本論文提出的良率分析架構於實際晶圓半導體廠的資料驗證中,同時考量了分析效率、週期時間與良率的離群值效應、共變量效應以及非線性相關效應,找出影響良率的關鍵因子。此良率分析架構不僅可以提供工程師影響良率關鍵的因子,亦可提供這些關鍵因子額外的資訊。
In semiconductor manufacturing, yield loss is not only due to impropriate settings of individual process recipes but also associated with longer cycle time. On the one hand, wafer lot in some specific process steps with longer cycle time is more likely to be contaminated by particles or oxidized. On the other hand, an abnormal event sometime may result in low yield with longer cycle time. Therefore, cycle time has become either a direct or indirect factor to yield loss. Using cycle time data for yield analysis is a new topic in semiconductor manufacturing. There are four challenges for cycle time analysis. The 1st challenge, C1, is high computation complexity because, with hundreds of process steps nowadays, the number of cycle time partitioned by different process steps is huge. The 2nd challenge, C2, is the outlier effect between cycle time and yield. It is inevitable and may decrease the quality of cycle time analysis. The 3rd challenge, C3, is that cycle time is not the only possible yield loss factor. Without considering other covariate effect may mislead the result of the analysis. The 4th challenge, C4, is the nonlinear correlation between cycle time and yield. Without considering the nonlinear correlation effect may reduce the variation explanation capability of a yield analysis model. To cope with the four challenges C1~C4, a methodology framework of cycle-time-aware yield analysis is proposed in this thesis. It consists of three major modules: critical cycle time analysis (CCA), tool commonality analysis (TCA) and integrated yield modeling (IYM). The first module, CCA, sequentially conducts Screening and Identification to solve challenges C1 and C2 respectively. The Screening aims at efficiently highlighting the cycle time strongly associated with yield by using approximated Pearson correlation coefficient, whereas Identification shoots for robustly providing the cycle time significant to yield loss by applying Spearman correlation coefficient, a nonparametric correlation analysis approach. The second module, TCA, adopts an industry practice, one-against-others ANOVA (Analysis of Variance) technique, to highlight the equipment tool significant to yield loss. The third module, IYM, collaborates with CCA and TCA by applying stepwise regression with piecewise linear modeling to solve challenges C3 and C4. Simulation study is conducted on CCA, which shows that the efficiency of approximated Pearson correlation coefficient outperforms the efficiency of standard Pearson correlation coefficient while maintaining the same accuracy of identification rate. Fab data validation demonstrates that the proposed method not only identifies several yield-loss factors but also reveals both nonlinear correlation and covariate effects of cycle time. Engineers thus benefit from obtaining additional information on the relationship among individual key factors for effective yield analysis.