- 學位論文
A Fully Cell-Based Design for Measuring Memory Timing Parameters
以標準細胞原件庫設計之記憶體時序量測電路
摘要
Nowadays, almost all the eletronic products have memories inside. If we don’t have the timing information of these memories, we cannot define the products’ specification. Tranditionally we use test machine to measure these timing information. However, some tester’s equipment delay will cause measurement error, such as channel delay, probe delay, and so on. Besides, for a system-on-chip (SOC) design, it’s not easy to probe the I/O signal of internal memories directly. Hence we need an embedded solution. This work presents a scheme that can measure timing parameters of a memory’s I/O interface. It can measure the setup/hold time and access time of the memory. To measure setup/hold time, we use a valid signal to restrict correct input value within a valid window. We can measure setup/hold time by adjusting the timing relation between clock and the valid window. In access time measurement, we use a time-to-digital converter (TDC) to measure the access pulse. The TDC can record the maximum timing pulse, so we can apply complete test pattern and get the worst access time in the end. We also propose calibration scheme for setup/hold time measurement and access time measurement individually. This design is constructed by standard cells, so it’s easy to transfer to another process technology. We implement it in TSMC 0.18nm CMOS technology. Simulation results shows that the setup/hold time error is less than 2.4% / 7.5%, the access time error is less than 4.4%, and area overhead is about 6.2% when the memory size is 4096x64.
並列摘要
在現今的電子產品當中，幾乎所有的產品都會有記憶體元件在晶片中。如果我們沒有記憶體相關的時序參數，將會很難對產品下定規格。傳統上會使用測試機台對記憶體的時序參數做量測。然而，一些測試機台的周邊器材，像是探針以及與晶片之間連接的傳輸線等等，都會造成一些額外的延遲時間，這會導致量測結果的誤差。另外，針對系統晶片(system-on-chip)，我們很難直接存取內部記憶體的輸入輸出訊號。因此我們需要一個內嵌式解決方案。在這篇論文裡面，我們提出一種能量測記憶體時序參數的架構。它能夠量測準備/保持時間 (setup/hold Time) 以及存取時間(access time)。在準備/保持時間的量測，我們使用有效訊號(valid signal)來使輸入訊號只會在有效窗口(valid window)中輸入正確的值。我們可藉由調整有效窗口與時脈訊號之間的時序關係，來量測出準備/保持時間。在存取時間量測的部分，我們使用一個時間至數位轉換器 (time-to-digital converter)。它能夠記錄最差情況的結果，因此我們能夠跑完完整的測試之後，最後得到最壞情況的存取時間。我們也針對準備/保持時間以及存取時間的量測提出校準方案(calibration scheme)。這份電路完全是以標準元件所組成，因此很容易轉移到期它製程上。我們以 TSMC 0.18um製程來實現，實驗結果顯示準備時間/保持時間的誤差在2.4% / 7.5%內，存取時間的誤差在4.4%以內。在使用4096x64的記憶體時，僅有6.2%額外面積代價。