摘要
隨著製程的演進，通訊系統的模擬速度也隨之提高。在效能方面，相較於傳統以軟體方式在通訊傳輸通道的模擬，硬體的方式可以提高到幾個數量級的傳輸速度。而外加高斯雜訊 (Additive White Gaussian Noise) 產生器在通訊系統上是一個非常重要的角色。 高斯雜訊(Gaussian noise)是具有正規(高斯)分布(normal distribution)的隨機變數(random variable) ，其平均數(mean)為0、 標準差為1。產生高斯雜訊的演算法主要有五種: 立固瑞定理 (Ziggurat method)、中央極限定理 (Central Limit Theorem)、華勒斯定理(Wallace method)、巴克斯-米勒定理 (Box-Muller algorithm)以及極性定理(Polar method) 。主要是利用線性回授位移暫存器(LFSR，linear feedback shift register)先產生虛擬隨機序列，以這些序列當作種子再經過上述的演算法來產生出高斯雜訊 高斯雜訊產生器主要是用在可程式化邏輯閘陣列 (FPGA) 晶片的傳輸系統通道模擬上。目前使用的方法是將 Box-Muller 演算法以及中央極限定理兩者結合而成的，這種方法的好處是能夠得到一個高精確度、高速度以及在硬體要求比較低的高斯雜訊產生器。而這篇論文所要提出來的方法是利用對數函數的指數律特性、三角函數的對稱性及週期性的特性所產生的高斯雜訊產生器 (WGNG)。這種方法可以得到一個在功率消耗上比較低但是晶片面積比較大的WGNG。這個AWGN 產生器的架構以及其效能分析將會在後面提出來。這篇論文主要是以標準數位設計流程設計出高斯雜訊產生器，在點18製程下提出架構，這個架構可以達到每秒 100M 樣本的輸出頻率。
關鍵字
高斯雜訊產生器並列摘要
Hardware emulation of communication channels can speed up the process of estimating the performance of a communication system by a few orders of magnitude compared with traditional software-based estimations. The noise generator can be used as a key component in a hardware-based simulation system, such as for exploring channel A hardware White Gaussian Noise Generator (WGNG) is developed for mobile communication channel emulation in FPGA circuit. High accuracy, fast and low-cost hardware are reached by combining the Box-Muller and Central limit methods Compared to existing methods, the proposed method costs lower power but more area. The architecture and the performance analysis of our AWGN generators are elaborated. A design for a White Gaussian Noise Generator (WGNG) is modified and implemented as a 0.18-μm CMOS digital ASIC for high-speed communication channel emulation. A layout is generated based on a standard digital design flow provided by Canadian Microelectronics Corporation (CMC). This implementation achieves an output rate of 100M samples/sec, which exceeds the speed of the original FPGA implementation by more than four times.
參考文獻
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