128Mb NOR型快閃記憶體之高速低雜訊系統讀取設計

A High-Speed and Low-Noise Readout Scheme for 128Mb NOR-type Flash Memories

陳泳旭(YungHsu Chen)

指導教授 ： 金雅琴

國立清華大學/電機資訊學院/電子工程研究所/碩士(2008年)

https://doi.org/10.6843/NTHU.2008.00006

摘要

本論文將設計一個適用於NOR型128Mb快閃記憶體的高速與低雜訊的讀取裝置。在NOR型快閃記憶體相較於NAND型快閃記憶體最大優勢在於讀取速度，因此，NOR型Flash memory之讀取速度就顯的特別的重要。在成本的考量下，記憶元件陣列的字線長度通常不能切割得太短，而讀取速度會受限於陣列中的字線長度，也就是字線的設定時間。在這些先天條件的限制下，感測放大器的設計就顯得相當的重要。在最短的時間內正確得讀取記憶體陣列中所儲存的資料，必須要屏除所有可能造成讀取錯誤的雜訊干擾；由電路分析得知，最多雜訊的地方就是輸出緩衝器和感測放大器本身。本論文研究重點在於應用預設電路的觀念減少這些雜訊對感測放大器的干擾並提升讀取速度，另外在128Mb NOR型Flash memory陣列中，實際分析產品跑線之電阻電容的效應，以及如何降低它們對速度的影響。以本論文的設計，TCE (chip enable time)/TAA (address access time)的速度可以從85nsec提升到80nsec，改善了5.88%，硬體面積增加不到0.017%，另外對TPA (page access time)也可從21nsec微幅提升到20nS，改善了4.76%。所設計改善讀取速度之電路經MXIC F13S 3P3M製程驗證，實際晶片量測結果符合設計預期。

關鍵字

快閃記憶體 ； 高速低雜訊 ； 讀取電路 ； 預設電路 ； 輸出雜訊 ； 雜訊干擾

並列摘要

In this thesis, a high-speed and low-noise readout scheme for the 128Mb NOR-type Flash memories was designed. It has a higher readout speed than the NAND-type Flash memories. Based on cost considerations, the word lines (WL) in the memory array are maintained at a maximum length to minimize cell area, while the read speed is usually limited by the WL RC delay, i.e., the WL setup time. As a result of these constraints, the overall memory performance of a good sense amplifier as well as its sensing scheme can be greatly affected. In order to enhance the readout speed, all the noises that can possibly cause reading error must be eliminated or suppressed. It was found that the output buffers and the sense amplifier generate most of the noises. In this thesis, the read speed was improved by reducing the noise through a presetting scheme. Due to the large memory array of 128Mb chips, the parasitic resistance and capacitance were also considered critical to the read speed. With the new readout scheme, the TCE (chip enable time) and TAA (address access time) were improved from 85nsec to 80nsec during the simulation tests, with an added overhead in chip area of less than 0.02%. Moreover, the TPA (page access time) also improved by 4.76%, from 21nsec to 20nsec. The new readout circuit and operational scheme was verified using silicon through a 3P3M process and the results achieved the original design targets.

並列關鍵字

flash memory ； high speed low noise ； read scheme ； preset circuit ； output noise ； noise disturb

參考文獻

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