- 學位論文
矽基材微型電感製備與特性分析
Fabrication and characterization of micro inductors on silicon substrate
摘要
為縮小通訊高頻元件體積，整合主動與被動元件是未來的技術趨勢。主動元件主要使用低電阻率的矽晶圓，然而在微波頻率下低電阻率的矽晶圓會對電感造成嚴重的能量損耗而使電感的品質因子降低，因此本研究重點在於提升電感元件之品質因子與電感值密度。為降低基材損耗提升品質因子，本研究採用包含增加介電材料的厚度，使用低介電常數的材料與懸空結構，以及加大電鍍銅膜厚度來降低導線的串聯電阻等方式;而在微型電感結構設計方面，則包括各種平面與懸空螺旋電感與螺線管電感結構等。由於電感幾何形狀對其高頻特性有相當大的影響，因此本研究亦設計不同尺寸的電感並且研究尺寸變化對高頻特性的影響。另外，傳統提升電感元件的電感值密度方式主要為增加電感的圈數，然而增加電感的圈數雖然可以提升電感值密度但卻同時增加了面積與基板寄生效應。雙層電感的架構雖可提升電感感值密度，但因層與層之間的寄生電容將導致較低的電感品質因子，因此製作大層間距之雙層懸空電感，除可有效降低層間的寄生電容提升品質因子外也可以提升其電感值密度。另ㄧ種提升電感感值密度的方式則是將磁性材料與電感整合，雖然加入磁性材料會使電感元件的電阻增加而降低電感的品質因子，但是卻可以有效的提升其電感值。由於加入磁性材料並不會增加電感的面積，因此可以增加其電感值密度並節省元件面積。除了改進電感的效能之外，另一個值得研究的領域為建立適當的元件電路模型來預測電感元件的效能，在此採用ㄧ螺旋形電感測試結構的等效電路模型，以數值分析的方式配合電感的尺寸與材料參數預測方形或圓形螺旋形電感的品質因子與電感值。此外，在螺線管結構電感方面，則提出一等效電路模型，單純利用材料參數與電感的幾何結構參數來計算螺線管電感的品質因子與電感值。
關鍵字
電感並列摘要
In order to reduce the size of high-frequency communication devices, the general technology trend is to integrate both the active and passive components in the same substrate. The active components are generally fabricated on low resistivity silicon substrate. However, silicon-based on-chip inductors usually suffer serious quality factor degradation at high frequency due to capacitive coupling in silicon substrates. Therefore, the goal of the study is to focus on how to improve the quality factor and inductance density of Si-based inductors. In order to reduce inductor’s substrate loss, we use thick low-k dielectric or air-bridge technology to isolate the silicon substrate as well as thick electroplating copper to reduce the series resistance of the inductor. Since the inductance and quality factor also depend on the dimensions of inductors, we have designed inductors with various dimensions to study the relationship between inductors’ properties and their physical dimensions. For conventional planar spiral inductors, the way to raise the inductance-to-area ratio is to increase the number of metal turns. However, the cost to be paid is the increased parasitic capacitance and the reduced quality factor of the spiral inductors. A double-level inductor fabricated by standard integrated circuits technology has been proposed to increase the inductance density. Nevertheless, it has low quality factor mainly due to the severe parasitic capacitance between conductor levels. Therefore, we fabricate double-level suspended inductors with large inter-level spacing, which can effectively reduce the parasitic capacitance and result in high quality factor. The other way to enhance inductance density is to integrate magnetic materials with inductors. Although inductors with magnetic materials have better inductance, they have a decreased quality factor due to the increasing series resistance. In addition to the inductor’s property enhancement, an appropriate device circuit model for predicting inductor’s properties is also important. One approach employed here is to utilize a data fitting technique to obtain the series inductance and resistance values of a spiral inductor. The other equivalent circuit components are calculated from the materials properties and physical dimensions of the inductor. Therefore, the designers would be able to determine quickly the inductor properties of the spiral inductors of interests from the results of the limited tested structures. The other inductor’s physical model is devised for simulating the properties of solenoid inductors. All the inductive, resistive, and capacitive equivalent circuit elements can be correlated to the physical parameters and material properties of the solenoid inductors.