- 學位論文
針對以MLC STT-MRAM作為主記憶體有著非對稱性寫入能源的系統所提出的重思考末級快取寫回策略
Rethinking Last-level-cache Write-back Strategy for MLC STT-MRAM Main Memory with Asymmetric Write Energy
摘要
為了達成低能源消耗的需求，又因為MLC STT-MRAM有高記憶體單元密度、可與DRAM相匹敵的讀寫效能以及沒有更新耗能，所以它被廣泛地認為是在下一世代電腦架構中可以取代以DRAM為基底建構主記憶體的一個夠格的候選者。然而，MLC STT-MRAM在進行寫入操作時會消耗比DRAM更多的能源，這是因為有時候MLC STT-MRAM會需要兩個轉換步驟才能將原本儲存的資料改變成想要寫入的目標資料。也正因如此，當不同的bit patterns被寫入到記憶體單元時，MLC STT-MRAM所消耗的能源也不一樣。據我們所知，之前的研究為了達到減少主記憶體耗能，而在電腦系統裡利用STT-RAM作為主記憶體時幾乎都沒有考慮到非對稱性能源消耗的特性。因此，我們提出了一個energy-aware cache replacement policy，稱為energy-aware write-back strategy (EWS)，它會將非對稱性能源消耗納入考慮，因此每當快取失誤發生時，它都能從中選出一個最適合的快取區塊從快取中踢除以作替換，也因此達到最小化系統能源消耗的目的。實驗結果顯示，跟LRU相比，我們所提出得解決方案平均來說可以減少23.9%能源消耗量。
並列摘要
To meet the requirement of low-power consumption, multi-level-cell STT-RAM (MLC STT-RAM) has been widely regarded as a potential candidate for replacing DRAM-based main memory in the next generation computer architectures because of its high cell density, comparable read/write performance and zero refresh power consumption. However, MLC STT-MRAM has higher power consumption than DRAM while a write operation is performed because MLC STT-MRAM sometimes needs to perform a two-step transition to change the original stored bits to another specific written bit patterns. As a result, MLC STT-MRAM has asymmetric power consumption while different bit patterns are written to a memory cell. To the best of our knowledge, a few or none of previous studies consider the feature of asymmetric power consumption to reduce main memory power consumption while STT-RAM is utilizes as a main memory in a computer system. Thus, this study proposes an energy-aware cache replacement policy, namely energy-aware write-back strategy (EWS), which consider asymmetric energy consumption to evict a proper cache block, so as to minimize system energy consumption. The experimental results show that the proposed solution reduces the energy consumption by 23.9% on average, compared with LRU.