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  • 學位論文

機械應力引致類比元件及金氧半場效電晶體電性特性漂移與變動之研究

Investigation of the Mechanical Stress-Induced Shift and Variation of Electrical Characteristics in the Analogic Device and MOSFETs

指導教授 : 江國寧
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摘要


晶片的設計與製程日漸精細化與複雜化,對電性要求也愈趨嚴謹,在半導體電子元件整個設計與製造的過程中,因設計不良或製程所引致的機械應力效應,將直接影響元件本身的功能與品質。元件的電性特性,在晶片經過後續相關製程之後,諸如,構裝等,可能造成嚴重的電性特性變化。其中尤以機械應力引致元件電性特性的不穩定與漂移變化,對於元件整體效能的影響甚巨,是一個非常重要且必須深入研究的課題。本研究主要針對兩方面進行探討,於構裝層面研究探討低壓降穩壓晶片於構裝後因各構裝材料熱膨脹係數不同所造成的機械應力(應變)效應,對於電性特性的影響,諸如,輸出電壓變化。研究規劃有八種不同的低壓降穩壓晶片構裝樣品進行實驗,以了解機械應力對晶片電性特性之影響。由於金氧半場效電晶體元件廣被使用於半導體電子元件中,因此於元件層面則以金氧半場效電晶體元件為研究對象,探討在機械應力(應變)效應對於其電性特性的影響。研究將探討不同的元件尺寸與佈放方向受到不同的機械應力之下,其電性特性受到機械應力影響而變動的程度,諸如,元件通道飽和汲極電流變化與臨界電壓變化的變化等。實驗結果顯示,於構裝層面實驗中,晶片表面有塗佈機械應力緩衝層時(不論是聚亞醯胺或高分子聚合物),其輸出電壓特性的變化較小。但若晶片表面無任何塗佈機械應力緩衝層時,則其輸出電壓特性的變化較大。且對於構裝體而言,若整體構裝體幾何尺寸不對稱,則構裝過程中所引致的機械應力效應較大,因此晶片之輸出電壓特性之變化大。由於聚亞醯胺是在前段晶圓製造時以全面性晶圓塗佈的方式作業,其缺點為塗佈厚度較薄,僅數微米,因此抵抗機械應力的能力較弱。而高分子聚合物則是於後段晶片構裝時以個別單顆晶片塗佈的方式作業,不適用於小型構裝體,其優點為塗佈厚度較厚,可達數十至數百微米,因此抵抗機械應力的能力較佳。 於元件層面實驗中,不論是N型或P型金氧半場效電晶體元件,當其通道方向(電流方向)與機械應力施加方向平行時,元件電性特性對於機械應力效應的敏感度最大,因此汲極電流變化最大。由汲極電流變化與載子遷移率變化的關係式可知,汲極電流變化與載子遷移率變化成正比,因此,汲極電流變化大也表示載子遷移率變化大。另外,對於N型金氧半場效電晶體元件而言,汲極電流變化最小的情況是發生在當其通道方向與機械應力施加方向垂直時,而對於P型金氧半場效電晶體元件,汲極電流變化最小的情況是發生在當其通道方向與機械應力施加方向成±45度時。此外,P型金氧半場效電晶體元件在其通道方向與機械應力施加方向成±45度時,其汲極電流變化在所有實驗元件樣品組中為最小,其趨勢斜率幾近水平。由實驗結果可知,在晶片設計中, N型金氧半場效電晶體元件佈放時以其通道方向與機械應力施加方向垂直最佳,而P型金氧半場效電晶體元件佈放時以其通道方向與機械應力施加方向成±45度時最佳,如此可得最小的遷移率變化量,因此可降低元件受機械應力的影響避免造成晶片效能的降低。在臨界電壓的實驗中,N型與P型金氧半場效電晶體元件在不同的張/壓應力下,其臨界電壓變化皆小於±0.5%,此意謂元件臨界電壓受機械應力的影響非常微小,可予以忽略。本研究的實驗結果相較於文獻,呈現一致性,其中微小的差異可歸因於因製程所造成的元件氧化層差異、摻雜濃度的不同及量測誤差等所造成。本研究於構裝層面與元件層面上深入探討釐清其力學行為模式,確定晶片表面的機械應力狀態,及其與構裝結構、製程及材料之間的關係,經由以上之流程,吾人即可建立起一晶片設計之研究法則。故本研究不論是在學術研究上或是實際應用上,皆具有相當之價值。基於本研究的實驗結果,可發展一完整的晶片設計法則並探討構裝結構設計與選用準則,以大幅降低機械應力效應的對於晶片影響,藉以增進並改善晶片的效能。本研究並發展一套獨創性的力學模型,用以闡釋N型與P型金氧半場效電晶體在機械應力作用下,其載子遷移率的變化。此力學模型對於載子遷移率變化之物理圖像的描述較一般的能帶模型更為簡潔清晰,易於理解。

並列摘要


Recently, the integrated circuit trends to have more and more complex with multi-functions but smaller and smaller in size. For this reason, it needs much more exact calculation and desination for electrical characteristics. Poor design and process-induced mechanical stress effect cause serious problem during fabrication stages, especially for the packaging process in the front-end process, which make more variation to electrical characteristics and affect the quality and performance of the device in the end. Mechanical stress induced unstable and variation of electrical characteristics is one of the major factors to affect the entire performance of a device seriously. So, the mechanical stress always the most important and urgent factor to be deeply investigated. In order to understand the variation of electrical characteristics under the mechanical stress effect in the chip, two different research topics, package and device level, were investigated in this research. In package level, four different samples, polyimide with/without polymer coated and non-polyimide with/without polymer coated, in low-dropout chips were all packaged into two different packages, small outline package and quad flat non-lead package. In this level, overall eight different samples were prepared and submitted to experiment. In the device level, N- and P-MOSFETs were prepared for investigation the relationship between the mechanical stress effect and electrical characteristics. In package level, the variation of chip output voltage is smaller when with stress buffer layer (polyimide or polymer) but was larger when chip without any stress buffer layer. The chip was seriously affected by the package-induced mechanical stress in a package with unsymmetrical geometry, as the output voltage variation was larger. Because the polyimide coating was applied on surface of whole wafer in the front-end wafer fabrication, the capability of the stress buffer was weaker due to the thickness of the polyimide layer was only few micometers thin. Furthermore, the polymer coating was applied on the chip one by one in the back-end packaging process, the advantage is the capability of the stress buffer was stronger due to the thickness of the polymer layer is from decades to hundred of micrometers, the drawbacks are unsuotable for the small package. In device level, both in N- and P-MOSFETs, their electrical characteristics are more sensitive to the mechanical stress when the direction of the device channel (current flow) was parallel to the orientation of applied mechanical stress, which then caused high variation of the drain current. In addition, for N-MOSFETs, the drain current variation is small when the direction of the device channel was perpendicular to the orientation of applied mechanical stress. However, for P-MOSFETs, smallest drain current variation occurred when the angle is in ±45 degrees, the slope was similar to the horizontal. In the IC design field, for obtaining the minimum mobility variation under the applied mechanical stress, the best layout of the direction of N-MOSFETs was the device channel perpendicular to the orientation of applied mechanical stress, but in ±45 degrees for P-MOSFETs. The threshold voltage variations of all samples under different mechanical stresses were under 0.5%, that means the threshold voltage was almost not affected by mechanical stress. The experimental results of the drain current variation and threshold voltage variation in this research were well agree with prior studies, the slight subtle difference could be attributed to the gate-oxide variation, different doping concentration and measuring error and others. My research provides a very useful design guideline of MOSFETs for the integrated circuit and a criterion of package design and selection to reduce the mechanical stress effect to improve the performance of the chip, which is very valuable in both academic and economic applications. Furthermore, a series of originative models on mechanics are developed from this research for describing the carrier mobility change of MOSFETs under mechanical stresses. The originative models in this research on mechanics provide more concise and clear descriptions of physical models for the change of the carrier mobility in MOSFETs. Therefore, the models might easier be understood than the general energy band models.

參考文獻


1. E. Wigner and F. Seitz, “On the constitution of metallic Sodium,” Physical Review, Vol. 43, pp. 804-810, May 1933.
2. E. Wigner and F. Seitz, “On the constitution of metallic Sodium. II,” Physical Review, Vol. 46, pp. 509-524, Sept. 1934.
3. E. Wigner, “On the interaction of electrons in metals,” Physical Review, Vol. 46, pp. 1002-1011, Dec. 1934.
4. F. Seitz, “The theoretical constitution of metallic Lithium,” Physical Review, Vol. 47, pp. 400-412, Mar. 1935.
5. J. Bardeen, “An improved calculation of the energies of metallic Li and Na,” Journal of Chemical Physics, Vol. 6, pp. 367-371, Jul. 1938.

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